A Multiband Low Noise Amplifier for Software Defined Radio Using Switchable Active Shunt Feedback Input Matching

Radio frequency (RF) receivers are the key front-end blocks in wireless devices such as smartphones, pagers, PDAs etc. An important block of the RF receiver is the Low-noise amplifier. It’s function is to amplify with little noise addition, the RF signal received at the atenna. Modern wireless devices for example the smartphone, incorporates multiple functionalities supported by various RF standards- GPS, Bluetooth, Wifi, GSM etc. Thus, the current trend in the wireless technology is to integrate radio receivers for each RF standard into a single system-on-chip (SoC) in order to reduce cost and area of the devices. In view of this, multiband RF receivers have been developed which feature multiband LNAs. This thesis presents the design and implementation of a multiband LNA for Software Defined Radio Applications. In this thesis, basic radio-frequency concepts are discussed which is followed by a discussion of pros and cons of various multistandard low-noise amplifier topologies. This is then followed by the design of the proposed reconfigurable LNA. The LNA is designed and fabricated in IBM 0.18um CMOS technology. It is made up of dual LC resonant tanks, one to switch between 5.2GHz and 3.5GHz frequency bands and the other, to switch between 2.4GHz and 1.8GHz bands. The input matching of the LNA is achieved using a switchable shunt active feedback network. The LNA achieves S21 of between 10.1dB and 13.43dB. It achieves an input matching (S11) between -13.44 dB and -11.97 dB. The noise figure measured ranges from 2.8 dB to 4.3 dB. The LNA also achieves an IIP3 from -7.12 dBm to -3.45 dBm at 50 MHz offset. The power consumption ranges from 7 mW to 7.2 mW

A Differential 4-Path Highly Linear Widely Tunable On-Chip Band-Pass Filter

A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3dB bandwidth of 35MHz and can be tuned from 100MHz up to 1GHz. IIP3 is better than 19dBm, P1dB=2dBm and NF<;5.5dB at Pdiss=2mW to 16mW.\u

High Performance Integrated Circuit Blocks for High-IF Wideband Receivers

Due to the demand for high‐performance radio frequency (RF) integrated circuit design in the past years, a system‐on‐chip (SoC) that enables integration of analog and digital parts on the same die has become the trend of the microelectronics industry. As a result, a major requirement of the next generation of wireless devices is to support multiple standards in the same chip‐set. This would enable a single device to support multiple peripheral applications and services. Based on the aforementioned, the traditional superheterodyne front‐end architecture is not suitable for such applications as it would require a complete receiver for each standard to be supported. A more attractive alternative is the highintermediate frequency (IF) radio architecture. In this case the signal is digitalized at an intermediate frequency such as 200MHz. As a consequence, the baseband operations, such as down‐conversion and channel filtering, become more power and area efficient in the digital domain. Such architecture releases the specifications for most of the front‐end building blocks, but the linearity and dynamic range of the ADC become the bottlenecks in this system. The requirements of large bandwidth, high frequency and enough resolution make such ADC very difficult to realize. Many ADC architectures were analyzed and Continuous‐Time Bandpass Sigma‐Delta (CT‐BP‐ΣΔ) architecture was found to be the most suitable solution in the high‐IF receiver architecture since they combine oversampling and noise shaping to get fairly high resolution in a limited bandwidth. A major issue in continuous‐time networks is the lack of accuracy due to powervoltage‐ temperature (PVT) tolerances that lead to over 20% pole variations compared to their discrete‐time counterparts. An optimally tuned BP ΣΔ ADC requires correcting for center frequency deviations, excess loop delay, and DAC coefficients. Due to these undesirable effects, a calibration algorithm is necessary to compensate for these variations in order to achieve high SNR requirements as technology shrinks. In this work, a novel linearization technique for a Wideband Low‐Noise Amplifier (LNA) targeted for a frequency range of 3‐7GHz is presented. Post‐layout simulations show NF of 6.3dB, peak S21 of 6.1dB, and peak IIP3 of 21.3dBm, respectively. The power consumption of the LNA is 5.8mA from 2V. Secondly, the design of a CMOS 6th order CT BP‐ΣΔ modulator running at 800 MHz for High‐IF conversion of 10MHz bandwidth signals at 200 MHz is presented. A novel transconductance amplifier has been developed to achieve high linearity and high dynamic range at high frequencies. A 2‐bit quantizer with offset cancellation is alsopresented. The sixth‐order modulator is implemented using 0.18 um TSMC standard analog CMOS technology. Post‐layout simulations in cadence demonstrate that the modulator achieves a SNDR of 78 dB (~13 bit) performance over a 14MHz bandwidth. The modulator’s static power consumption is 107mW from a supply power of ± 0.9V. Finally, a calibration technique for the optimization of the Noise Transfer Function CT BP ΣΔ modulators is presented. The proposed technique employs two test tones applied at the input of the quantizer to evaluate the noise transfer function of the ADC, using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed‐mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal‐to‐Quantization Noise Ratio (SQNR) performance is extracted via Least‐ Mean Squared (LMS) software‐based algorithm. Since the two tones are located outside the band of interest, the proposed global calibration approach can be used online with no significant effect on the in‐band content

Design of zigbee transmitter for IEEE 802.15.4 standrad

ZigBee is a standard defines a set of communication protocols for low-data-rate short-range wireless networking. ZigBee-based wireless devices operate in 868 MHz, 915 MHz, and 2.4 GHz frequency bands. The maximum data rate is 250 K bits per second. ZigBee is mainly for battery-powered applications where low data rate, low cost, and long battery life are main requirements. This thesis explores low power RFIC design for various blocks in Zigbee Transmitter. Zigbee RFTransmitter Comprises of Low Pass Filter, Variable Gain Amplifier, Up conversion Mixer and Power Amplifier. The proposed VGA is characterized by a wide range of gain variation The single-stage VGA is designed in UMC 0.18-u m CMOS technology and shows the maximum gain variation of 62 dB. The VGA dissipates 630 uA from 1.8-V supply while occupying (250 μm x 167.3 μm) of chip area. A low-voltage low-power and high linearity up-conversion mixer, designed in UMC 0.18-um RFCMOS technology is proposed to realize the transmitter front-end in the frequency band of 2.45 GHz. The proposed mixer can convert a 5 MHz intermediate frequency (IF) signals to a 2.45GHz RF signals, with a local oscillator at 2.45GHz. Simulation results demonstrate that at 2.45GHz, the circuit provides -11.30dB of conversion gain and the input-referred third-order intercept point (IIP3) of 35.16 dBm, output-referred third order intercept point(OIP3) of 12.88 dBm while drawing only 10mA for the mixer core under a supply voltage of 1.8 V. A low power Differential class A power amplifier is designed in the UMC 0.18um RFCMOS technology. The class A power amplifier provides 0 dBm output power with a power-added efficiency (PAE) of 22% and Power Gain of 10dB with 1.8V supply voltage. The dc power consumption is only 4.5mW. And all these blocks were integrated and simulated using Cadence© SpectreRF simulator in UMC-0.18um Mixed Signal CMOS RF models for the best simulation results

Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Design of a CMOS RF Front End Receiver in 0.18μm Technology

An RF front end receiver system refers to the analog down conversion stages of the wireless communication system. The Digital base-band signals cannot be transmitted directly through wireless channels due to the properties of electromagnetic waves. The baseband signals need to be converted to analog through a digital-to-analog converter (DAC), up converted to higher frequency using an up conversion mixer and then transmitted through the channel. The received signals are down converted to base band frequency and then converted to digital again using the analog to digital converter (ADC). The processes which the analog signal undergoes at the RF front end include amplification, mixing and filtering. The RF Front End receiver developed in this thesis makes use of a differential low noise amplifier (LNA) with center frequency at 1.75GHz. The incoming RF signal undergoes amplification by the LNA and is down converted by a Gilbert double balanced mixer to a first Intermediate frequency (IF) of 250 MHz A second Gilbert Double Balanced Mixer down converts to a low second IF of 50 MHz The local oscillator signal for the mixer is generated using a voltage controlled ring oscillator (VCO). The entire front end of the receiver was created in Cadence virtuoso schematic editor using CMOS 0.18μm technology. The total power consumed by the RF Front End Receiver is 113.36 mW