Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

The on-chip activities of any modern IC are always inhibited due to the occurrence of power supply noise (PSN) in the chip power line. From many decades, researchers are pondering on what are the major issue of this PSN occurrence and how it can be suppressed without interfering the actual chip functioning. In the course of time, it is found that the uncontrolled triggering of the on-chip system clock and the unguarded on-chip power line is instigating the two major factors for the occurrence of PSN i.e., i(t) → instantaneous current and di/dt → current ramp or the rate of change of current over time. Both i(t) and di/dt are also the sub-factors to rise the PSN components like resistive noise and inductive noise respectively. In this chapter, we light upon the occurrence of resistive and inductive noise as well as depict their individual impact on the PSN occurrences. There is also discussion on how PSN is suppressed over the years in spite of facing challenges in the execution of suppression techniques. This chapter even concludes on the suitable ways for mitigating PSN in the contemporary era of delivering complex on-chip features

High performance IC clock networks with grid and tree topologies

In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally intensive, large-scale design and optimization tasks for the generation and distribution of the clock signal through different topologies. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research. The synthesis and optimization methods for the two most commonly used clock topologies in IC design—the grid topology and the tree topology—are primarily investigated.The clock mesh network, which uses the grid topology, has very low skew variation at the cost of high power dissipation. Two novel clock mesh network designmethodologies are proposed in this dissertation in order to reduce the power dissipation. These are the first methods known in literature that combine clock meshsynthesis with incremental register placement and clock gating for power saving purposes. The application of the proposed automation methods on the emerging resonant rotary clocking technology, which also has the grid topology, is investigated in this dissertation as well.The clock tree topology has the advantage of lower power dissipation compared to other traditional clock topologies (e.g. clock mesh, clock spine, clock tree with cross links) at the cost of increased performance degradation due to on-chip variations. A novel clock tree buffer polarity assignment flow is proposed in this dissertation in order to reduce these effects of on-chip variations on the clock tree topology. The proposed polarity assignment flow is the first work that introduces post-silicon, dynamic reconfigurability for polarity assignment, enabling clock gating for low power operation of the variation-tolerant clock tree networks.Ph.D., Electrical Engineering -- Drexel University, 201

Multiparameter flow cytometry for the characterisation of extracellular markers on human mesenchymal stem cells

Extracellular surface proteins are used to identify fully-functional human mesenchymal stem cells (hMSCs) in a mixed population. Here, a multiparameter flow cytometry assay was developed to examine the expression of several bone marrow-derived hMSC markers simultaneously at the single cell level. The multiparameter approach demonstrates a depth of analysis that goes far beyond the conventional single or dual staining methods. CD73, CD90 and CD105 were chosen as positive markers as they are expressed on multipotent hMSCs, whilst CD34 and HLA-DR were chosen as negative indicators. Single colour analysis suggested a population purity of 100 %; in contrast, when analysed via the multiparameter method, the CD73/CD105/CD90/HLA-DR/CD34 phenotypes represented 94.5 ± 1.3 % of the total cell population. Also, although CD271 has been posited as a definite early stage hMSC marker, here we show it is not present on pre-passage cells, highlighting the need for careful marker selection. © 2013 Springer Science+Business Media Dordrecht

Supporting collaboration with non-literate forest communities in the congo-basin

Providing indigenous communities with ICT tools and methods for collecting and sharing their Traditional Ecological Knowledge is increasingly recognised as an avenue for improvements in environmental governance and socialenvironmental justice. In this paper we show how we carried out a usability engineering effort in the “wild” context of the Congolese rainforest – designing, evaluating and iteratively improving novel collaborative data collection interfaces for non-literate forest communities that can subsequently be used to facilitate communication and information sharing with logging companies. Working in this context necessitates adopting a thoroughly flexible approach to the design, development, introduction and evaluation of technology and the modes of interaction it offers. We show that we have improved participant accuracy from about 75% towards 95% and provide a set of guidelines for designing and evaluating ICT solutions in “extreme circumstances” – which hold lessons for CSCW, HCI and ICT4D practitioners dealing with similar challenges

The Role of Alpha-Band Brain Oscillations as a Sensory Suppression Mechanism during Selective Attention

Evidence has amassed from both animal intracranial recordings and human electrophysiology that neural oscillatory mechanisms play a critical role in a number of cognitive functions such as learning, memory, feature binding and sensory gating. The wide availability of high-density electrical and magnetic recordings (64–256 channels) over the past two decades has allowed for renewed efforts in the characterization and localization of these rhythms. A variety of cognitive effects that are associated with specific brain oscillations have been reported, which range in spectral, temporal, and spatial characteristics depending on the context. Our laboratory has focused on investigating the role of alpha-band oscillatory activity (8–14 Hz) as a potential attentional suppression mechanism, and this particular oscillatory attention mechanism will be the focus of the current review. We discuss findings in the context of intersensory selective attention as well as intrasensory spatial and feature-based attention in the visual, auditory, and tactile domains. The weight of evidence suggests that alpha-band oscillations can be actively invoked within cortical regions across multiple sensory systems, particularly when these regions are involved in processing irrelevant or distracting information. That is, a central role for alpha seems to be as an attentional suppression mechanism when objects or features need to be specifically ignored or selected against

Machine learning and DSP algorithms for screening of possible osteoporosis using electronic stethoscopes

Osteoporosis is a prevalent but asymptomatic condition that affects a large population of the elderly, resulting in a high risk of fracture. Several methods have been developed and are available in general hospitals to indirectly assess the bone quality in terms of mineral material level and porosity. In this paper we describe a new method that uses a medical reflex hammer to exert testing stimuli, an electronic stethoscope to acquire impulse responses from tibia, and intelligent signal processing based on artificial neural network machine learning to determine the likelihood of osteoporosis. The proposed method makes decisions from the key components found in the time-frequency domain of impulse responses. Using two common pieces of clinical apparatus, this method might be suitable for the large population screening tests for the early diagnosis of osteoporosis, thus avoiding secondary complications. Following some discussions of the mechanism and procedure, this paper details the techniques of impulse response acquisition using a stethoscope and the subsequent signal processing and statistical machine learning algorithms for decision making. Pilot testing results achieved over 80% in detection sensitivity

Multi-step Ahead Inflow Forecasting for a Norwegian Hydro-Power Use-Case, Based on Spatial-Temporal Attention Mechanism

Hydrological forecasting has been an ongoing area of research due to its importance to improve decision making on water resource management, flood management, and climate change mitigation. With the increasing availability of hydrological data, Machine Learning (ML) techniques have started to play an important role, enabling us to better understand and predict complex hydrological events. However, some challenges remain. Hydrological processes have spatial and temporal dependencies that are not always easy to capture with traditional ML models, and a thorough understanding of these dependencies is essential when developing accurate predictive models. This thesis explores the use of ML techniques in hydrological forecasting and consists of an introduction, two papers, and an application developed alongside the case study. The motivation for this research is to enhance our understanding of the spatial and temporal dependencies in hydrological processes and to explore how ML techniques, particularly those incorporating attention mechanisms, can aid in hydrological forecasting. The first paper is a chronological literature review that explores the development of data-driven forecasting in hydrology, and highlighting the potential application of attention mechanisms in hydrological forecasting. These attention mechanisms have proven to be successful in various domains, allowing models to focus on the most relevant parts of the input for making predictions, which is particularly useful when dealing with spatial and temporal data. The second paper is a case study of a specific ML model incorporating these attention mechanisms. The focus is to illustrate the influence of spatial and temporal dependencies in a real-world hydrological forecasting scenario, thereby showcasing the practical application of these techniques. In parallel with the case study, an application has been developed, employing the principles and techniques discovered throughout the course of this research. The application aims to provide a practical demonstration of the concepts explored in the thesis, contributing to the field of hydrological forecasting by introducing a tool for hydropower suppliers.Masteroppgave i Programvareutvikling samarbeid med HVLPROG399MAMN-PRO

Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew

An adiabatic charge pump based charge recycling design style

A typical CMOS gate draws charge equal to C[subscript L]Vdd2 from the power supply (Vdd) where C[subscript L] is the load capacitance. Half of the energy is dissipated in the pull-up p-type network, and the other half is dissipated in the pull-down n-type network. Adiabatic CMOS circuit reduces the dissipated energy by providing the charge at a rate significantly lower than the inherent RC delay of the gate. The charge can also be recovered with an RLC oscillator based power supply. However, the two main problems with adiabatic design style are the design of a high frequency RLC oscillator for the power supply, and the need to slow down the rate of charge supply for lower energy. This reduction in speed of operation renders this adiabatic technique inapplicable in certain situations. A new approach incorporating an adiabatic charge pump that moves the slower adiabatic components away from the critical path of the logic is proposed in this work. The adiabatic delays of a charge pump are overlapped with the computing path logic delays. Hence, the proposed charge pump based recycling technique is especially effective for pipelined datapath computations (digital signal processing, DSP, is such a domain) where timing considerations are important. Also the proposed design style does not interfere with the critical path of the system, and hence the delay introduced by this scheme does not reduce the overall computational speed. In this work, we propose one implementation schema that involves tapping the ground-bound charge in a capacitor (virtual ground) and using an adiabatic charge-pump circuit to feed internal virtual power supplies. As the design relies on leakage charge to generate virtual power supplies, it is most effective in large circuits that undergo considerable switching activity resulting in substantial charge tapping by the proposed scheme. The proposed method has been implemented in DSP applications like FIR filter, DCT/IDCT filters and FFT filters. Simulations results in SPICE indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% with no loss in performance, paving way for a new approach towards conserving energy in complex digital systems

Intelligent systems for efficiency and security

As computing becomes ubiquitous and personalized, resources like energy, storage and time are becoming increasingly scarce and, at the same time, computing systems must deliver in multiple dimensions, such as high performance, quality of service, reliability, security and low power. Building such computers is hard, particularly when the operating environment is becoming more dynamic, and systems are becoming heterogeneous and distributed. Unfortunately, computers today manage resources with many ad hoc heuristics that are suboptimal, unsafe, and cannot be composed across the computer’s subsystems. Continuing this approach has severe consequences: underperforming systems, resource waste, information loss, and even life endangerment. This dissertation research develops computing systems which, through intelligent adaptation, deliver efficiency along multiple dimensions. The key idea is to manage computers with principled methods from formal control. It is with these methods that the multiple subsystems of a computer sense their environment and configure themselves to meet system-wide goals. To achieve the goal of intelligent systems, this dissertation makes a series of contributions, each building on the previous. First, it introduces the use of formal MIMO (Multiple Input Multiple Output) control for processors, to simultaneously optimize many goals like performance, power, and temperature. Second, it develops the Yukta control system, which uses coordinated formal controllers in different layers of the stack (hardware and operating system). Third, it uses robust control to develop a fast, globally coordinated and decentralized control framework called Tangram, for heterogeneous computers. Finally, it presents Maya, a defense against power side-channel attacks that uses formal control to reshape the power dissipated by a computer, confusing the attacker. The ideas in the dissertation have been demonstrated successfully with several prototypes, including one built along with AMD (Advanced Micro Devices, Inc.) engineers. These designs significantly outperformed the state of the art. The research in this dissertation brought formal control closer to computer architecture and has been well-received in both domains. It has the first application of full-fledged MIMO control for processors, the first use of robust control in computer systems, and the first application of formal control for side-channel defense. It makes a significant stride towards intelligent systems that are efficient, secure and reliable