AN INCLUSIVE TEST PATTERN GENERATOR USING DATA VOLUME COMPRESSION

Because the BIST power consumption can certainly exceed the utmost ratings when testing as fast as possible, scan patterns should be shifted in a programmable low speed, and just the final couple of cycles and also the capture cycle are applied at its peak frequency. Within this paper, we advise a PRPG for LP BIST applications. The suggested hybrid solution enables someone to efficiently combine test compression with logic BIST, where both techniques could work synergistically to provide top quality test. Therefore, it is a really attractive LP test plan that enables for buying and selling-off test coverage, pattern counts, and toggling rates in an exceedingly flexible manner. Particularly, several hybrid BIST schemes store deterministic top-up patterns around the tester inside a compressed form, after which make use of the existing BIST hardware to decompress these test patterns. The bottom is thus provided by  observe that chain 45 isn't incorporated because it features just one specified scan cell. A high probability of manufacturing confirmed logic value inside a purely pseudorandom fashion is really a rationale behind excluding from the base scan chains hosting just one specified bit. Just like conventional scan-based test, hybrid schemes, because of the high data activity connected with scan-based test operations, may consume a lot more power than the usual circuit under-test is built to function under. The generator mainly is aimed at lowering the switching activity during scan loading because of its preselected toggling (PRESTO) levels. LP PRPG can also be able to serving as a completely functional test data decompress or having the ability to control scan shift-in switching activity through the entire process of encoding

A RANDOM TEST PATTERN GENERATOR WITH ENHANCED FAULT COVERAGE

Particularly, several hybrid BIST schemes store deterministic top-up patterns around the tester inside a compressed form, after which make use of the existing BIST hardware to decompress these test patterns. Just like conventional scan-based test, hybrid schemes, because of the high data activity connected with scan-based test operations, may consume a lot more power than the usual circuit under-test is built to function under. Because the BIST power consumption can certainly exceed the utmost ratings when testing as fast as possible, scan patterns should be shifted in a programmable low speed, and just the final couple of cycles and also the capture cycle are applied at its peak frequency. Within this paper, we advise a PRPG for LP BIST applications. The suggested hybrid solution enables someone to efficiently combine test compression with logic BIST, where both techniques could work synergistically to provide top quality test. Therefore, it is a really attractive LP test plan that enables for buying and selling-off test coverage, pattern counts, and toggling rates in an exceedingly flexible manner. The generator mainly is aimed at lowering the switching activity during scan loading because of its preselected toggling (PRESTO) levels. LP PRPG can also be able to serving as a completely functional test data decompress or having the ability to control scan shift-in switching activity through the entire process of encoding. The bottom is thus provided by  observe that chain 45 isn't incorporated because it features just one specified scan cell. A high probability of manufacturing confirmed logic value inside a purely pseudorandom fashion is really a rationale behind excluding from the base scan chains hosting just one specified bit

LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein

A MODIFIED FAULT COVERAGE ARCHITECTURE FOR A LOW POWER BIST TEST PATTERN GENERATOR USING LP-LFSR

This paper proposes low power pseudo random Test Pattern generation .This test pattern is run on the circuit under test for desired fault coverage. The power consumed by the chip under test is a measure of the switching activity of the logic inside the chip which depends largely on the randomness of the applied input stimulus. Reduced correlation between the successive vectors of the applied stimulus into the circuit under test can result in much higher power consumption by the device than the budgeted power. A new low power pattern generation technique is implemented using a modified conventional Linear Feedback Shift Register which can perform fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random patterns by reducing the hardware utilization. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit under Test (CUT) and hence power consumption is also reduced without any penalty in the hardware resources

Power Droop Reduction In Logic BIST By Scan Chain Reordering

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic BIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time

Scalable diversified antirandom test pattern generation with improved fault coverage for black-box circuit testing

Pseudorandom testing is incapable of utilizing the success rate of preceding test patterns while generating subsequent test patterns. Many redundant test patterns have been generated that increase the test length without any significant increase in the fault coverage. An extension to pseudorandom testing is Antirandom that induces divergent patterns by maximizing the Total Hamming Distance (THD) and Total Cartesian Distance (TCD) of every subsequent test pattern. However, the Antirandom test sequence generation algorithm is prone to unsystematic selection when more than one patterns possess maximum THD and TCD. As a result, diversity among test sequences is compromised, lowering the fault coverage. Therefore, this thesis analyses the effect of Hamming distance in vertical as well as horizontal dimension to enhance diversity among test patterns. First contribution of this thesis is the proposal of a Diverse Antirandom (DAR) test pattern generation algorithm. DAR employs Horizontal Total Hamming Distance (HTHD) along with THD and TCD for diversity enhancement among test patterns as maximum distance test pattern generation. The HTHD and TCD are used as distance metrics that increase computational complexity in divergent test sequence generation. Therefore, the second contribution of this thesis is the proposal of tree traversal search method to maximize diversity among test patterns. The proposed method uses bits mutation of a temporary test pattern following a path leading towards maximization of TCD. Results of fault simulations on benchmark circuits have shown that DAR significantly improves the fault coverage up to 18.3% as compared to Antirandom. Moreover, the computational complexity of Antirandom is reduced from exponential O(2n) to linear O(n). Next, the DARalgorithm is modified to ease hardware implementation for on-chip test generation. Therefore, the third contribution of this thesis is the design of a hardware-oriented DAR (HODA) test pattern generator architecture as an alternative to linear feedback shift register (LFSR) that consists of large number of memory elements. Parallel concatenation of the HODA architecture is designed to reduce the number of memory elements by implementing bit slicing architecture. It has been proven through simulation that the proposed architecture has increased fault coverage up to 66% and a reduction of 46.59% gate count compared to the LFSR. Consequently, this thesis presents uniform and scalable test pattern generator architecture for built-in self-test (BIST) applications and solution to maximum distance test pattern generation for high fault coverage in black-box environment

Efficient Test Compaction for Pseudo-Random Testing

Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo-randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature