Throughput-Centric Wave-Pipelined Interconnect Circuits for Gigascale Integration

The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.Ph.D.Committee Chair: Davis, Jeffrey; Committee Member: Kohl, Paul; Committee Member: Meindl, James; Committee Member: Swaminathan, Madhavan; Committee Member: Wills, D. Scot

High-Speed and Low-Energy On-Chip Communication Circuits.

Continuous technology scaling sharply reduces transistor delays, while fixed-length global wire delays have increased due to less wiring pitch with higher resistance and coupling capacitance. Due to this ever growing gap, long on-chip interconnects pose well-known latency, bandwidth, and energy challenges to high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, the increased complexity and high level of integration requires higher wire densities, worsening crosstalk noise and power consumption of conventionally repeated interconnects. Such increasing concerns in global on-chip wires motivate circuits to improve wire performance and energy while reducing the number of repeaters. This work presents circuit techniques and investigation for high-performance and energy-efficient on-chip communication in the aspects of encoding, data compression, self-timed current injection, signal pre-emphasis, low-swing signaling, and technology mapping. The improved bus designs also consider the constraints of robust operation and performance/energy gains across process corners and design space. Measurement results from 5mm links on 65nm and 90nm prototype chips validate 2.5-3X improvement in energy-delay product.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75800/1/jseo_1.pd

Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI)

The main objective of this research is to develop a pervasive wire sharing technique that can be easily applied across the entire range of on-chip interconnects in a very large scale integration (VLSI) system. A wave-pipelined multiplexed (WPM) routing technique that can be applied both intra-macrocell and inter-macrocell interconnects is proposed in this thesis. It is shown that an extensive application of the WPM routing technique can provide significant advantages in terms of area, power and performance. In order to study the WPM routing technique, a hierarchical approach is adopted. A circuit-level, system-level and physical-level analysis is completed to explore the limits and opportunities to apply WPM routing to current VLSI and future gigascale integration (GSI) systems. Design, verification and optimization of the WPM circuit and measurement of its tolerance to external noise constitute the circuit-level analysis. The physical-level study involves designing wire sharing-aware placement algorithms to maximize the advantages of WPM routing. A system-level simulator that designs the entire multilevel interconnect network is developed to perform the system-level analysis. The effect of WPM routing on a full-custom interconnect network and a semi-custom interconnect network is studied.Ph.D.Committee Chair: Davis, Jeffrey; Committee Member: Kohl, Paul; Committee Member: Lim, Sung Kyu; Committee Member: Meindl, James; Committee Member: Milor, Lind