Model Based Design Environment for the Embedded System Case Study: Inverter Power Supply

学位記番号：工博甲43

PWM Techniques: A Pure Sine Wave Inverter

The ever-increasing reliance on electronic devices which utilize AC power highlights the problems associated with the unexpected loss of power from the electrical grid. In places where the electrical infrastructure is not well-developed, brown-outs can prove fatal when electronic medical instruments become unusable. Therefore, there is a need for inexpensive and reliable pure-sine wave inverters for use with medical devices in the underdeveloped world. This report documents the development of one component of an uninterruptible power supply, the DC-to-AC inverter. The three-level PWM system within this report is created with the possibility of a feedback-regulated system to be implemented in the future

Основи схемотехніки електронних систем

Basics of circuitry are stated, principles of operation are considered, it is given calculations of analog, digital and pulse devices of electronic systems, based on semiconductor devices, integrated operational amplifiers and integrated logic circuits of TTL, MOS, CMOS types, construction principles of systems of control by electronics devices based on microprocessors and microcontrollers. For students of institutions of higher education. It can be useful for specialists on electronic engineering, specializing in the area of development, fabrication and maintenance of electronic systems and devices

Design and Simulation of an 8-Bit Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter

The thesis initially investigates the history of the monolithic ADCs. The next chapter explores the different types of ADCs available in the market today. Next, the operation of a 4-bit SAR ADC has been studied. Based on this analysis, an 8-bit charge-redistribution SAR ADC has been designed and simulated with Multisim (National Instruments, Austin, TX). The design is divided into different blocks which are individually implemented and tested. Level-1 SPICE MOSFET models representative of 5μm devices were used wherever individual MOSFETs were used in the design. Finally, the power dissipation during the conversion period was also estimated. The supply voltage for the ADC is 5V and the clock frequency is 500KHz

Black-Box Modelling of Nonlinear Audio Circuits

This Thesis details various black-box modelling techniques for nonlinear audio circuits. The aim of this work was to compare the different approaches and determine the current most accurate model. The models analysed were: Chebyshev polynomials, Hammerstein, polynomials of best fit and a parametric model. These implementations were compared based on their spectral accuracy and time-domain accuracy. From the analysis of these models, a new method is proposed. This proposed model restructures the determined most accurate black-box model by placing a nonlinearity between a high-pass and a low-pass filter. The filters emulate the linear response of the nonlinear circuit. These filters also have a reduced filter order in comparison to the linear response. The proposed method results in a model that performs close to the current best but does result in a massive reduction in computational time, up to 95% less time required and 99% fewer operations

Generalized Wave Digital Filter Realizations of Arbitrary Reciprocal Connection Networks

In this paper, an existing approach for modeling and efficiently implementing arbitrary reciprocal connection networks using wave digital (WD) scattering junctions based on voltage waves is extended to be used in a broader class of WD filters (WDFs) based on different kinds of waves. A generalized wave definition which includes traditional voltage waves, current waves, and power-normalized waves as particular cases is employed. Closed-form formulas for computing the scattering matrices of the junctions are provided. Moreover, the approach is also extended to the family of Biparametric WDFs, which have been recently introduced in the literature

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout

A SigmaDelta modulator for digital hearing instruments using 0.18 mum CMOS technology.

This thesis develops the design methodology for a low-voltage low-power SigmaDelta Modulator, realized using a switched op-amp technique that can be used in a hearing instrument. Switched op-amp implementation allows scaling down the design to the latest CMOS technology. A single-loop second-order SigmaDelta Modulator topology is chosen. The modulator circuit features reduced complexity, area reduction and low conversion energy. The modulator has a sampling rate of 8.2 MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16 kHz. The modulator is implemented in a 0.18 mum digital CMOS technology with metal-to-metal sandwich structure capacitors. The modulator operates with a supply voltage of 1.8 V. The active area is 0.403 mm2. The modulator achieves a 98 dB signal-to-noise-and-distortion ratio (SNDR) and a 100 dB dynamic range (DR) at a Nyquist conversion rate of 32 kHz and consumes 1321 muW with a joule/conversion figure of merit equal to 161 x 10-12 J/s. The design methodology is developed through the extensive use of simulation tools. The behaviour simulation is carried out using Matlab/SIMULINK while circuits are simulated with Hspice using the Cadence design tools. Full-custom layout for the analog and the digital circuits is performed using the Cadence design tool. Post-processing simulation of the extracted modulator with parasitic verifies that results meet the requirements. The design has been sent to CMC for fabrication. Source: Masters Abstracts International, Volume: 43-03, page: 0947. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications

Approximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization