Wake-Up Oscillators with pW Power Consumption in Dynamic Leakage Suppression Logic

In this paper, two circuit topologies of pW-power Hz-range wake-up oscillators for sensor node applications are presented. The proposed circuits are based on standard cells utilizing the Dynamic Leakage Suppression logic style [4]-[5]. The proposed oscillators exhibit low supply voltage sensitivity over a wide supply voltage range, from nominal voltage down to the deep sub-threshold region (i.e., 0.3V). This enables direct powering from energy harvesters or batteries through their whole discharge cycle, suppressing the need for voltage regulation. Post-layout time-domain simulations of the proposed oscillators in 180nm show a power consumption of 1.4-1.7pW, a supply-sensitivity of 55-40%/V over the 0.3V-1.8V supply voltage range, and a compact area down to 1,500μm2. The very low power consumption makes the proposed circuits very well suited for energy-harvested systems-on-chip for Internet of Things applications

A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply

In this paper, a pW-power relaxation oscillator for sensor node applications is presented. The proposed oscillator operates over a wide supply voltage range from nominal down to deep sub-threshold and requires only a sub-pF capacitor for Hz-range output frequency. A true pW-power operation is enabled thanks to the adoption of an architecture leveraging transistor operation in super-cutoff, the elimination of voltage regulation, and current reference. Indeed, the oscillator can be powered directly from highly variable voltage sources (e.g., harvesters and batteries over their whole charge/discharge cycle). This is achieved thanks to the wide supply voltage range, the low voltage sensitivity of the output frequency and the current drawn from the supply. A test chip of the proposed oscillator in 180 nm exhibits a nominal frequency of approximately 4 Hz, a supply voltage range from 1.8 V down to 0.3 V with 10%/V supply sensitivity, 8-18-pA current absorption, and 4%/°C thermal drift from -20 °C to 40 °C at an area of 1600 μm². To the best of the authors' knowledge, the proposed oscillator is the only one able to operate from sub-threshold to nominal voltage

A Sub-Leakage pW-Power Hz-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply

A pW-power versatile relaxation oscillator operating from sub-threshold (0.3V) to nominal voltage (1.8V) is presented, having Hz-range frequency under sub-pF capacitor. The wide voltage and low sensitivity of frequency/absorbed current to the supply allow the suppression of the voltage regulator, and direct powering from harvesters (e.g., solar cell, thermal from machines) or 1.2-1.5V batteries. A 180nm testchip exhibits a frequency of 4 Hz , 10%/V supply sensitivity at 0.3-1.8V, 8-18pA current, 4%/°C thermal drift from -20°C to 40°C

Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Analog processing by digital gates: fully synthesizable IC design for IoT interfaces

Analog integrated circuits do not take advantage of scaling and are easily the bottleneck in terms of cost and performance in Internet of Things (IoT) sensor nodes integrated in nanoscale technologies. While this challenge is most commonly addressed by devising more “digital friendly” analog cells based on traditional design concepts, the possibility to translate analog functions into digital, so that to implement them by true digital gates, is now emerging as a promising alternative. This last approach, which challenges the idea that “analog circuits will be always needed”, is presented in this tutorial starting from the theoretical background to its application in digital-based operational amplifiers, voltage references, oscillators and data converters integrated on silicon which have proposed in recent literature. The applicability of the concepts to the design of ICs which are natively portable across technology nodes and highly reconfigurable, thus enabling dynamic energy quality scaling, as well as a low design effort and a fast time-to-market will be described

A 300mV-Supply Standard-Cell-Based OTA with Digital PWM Offset Calibration

This paper introduces a fully digital pulse-width-modulation (PWM) based calibration technique intended to dynamically compensate the input offset voltage due to process and mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTA). Post-layout simulations on a DB-OTA circuit in 180nm featuring the proposed calibration technique demonstrate that process and mismatch related offset voltage can be effectively compensated by varying the duty cycle of a square wave signal with minimum performance overhead. The proposed OTA consumes just 7.34nW while driving a capacitive load of 80pF with a Total Harmonic Distortion lower than 2.26% at 100mV input signal swing. The total silicon area is 1,700 um^2

Relaxation Digital-to-Analog Converter with Foreground Digital Self-Calibration

3noA reference-free, fully digital foreground self-calibration strategy intended to automatically tune the clock frequency of Relaxation Digital to Analog Converters (ReDACs), as demanded for linear operation, is presented in this paper. The effectiveness of the proposed approach is demonstrated by computer simulations on a 10-bit, 2MS/s ReDAC designed in 40nm CMOS and operated from a 600mV power supply voltage. After the proposed calibration, the ReDAC is shown to operate near the optimal clock frequency achieving 0.98 LSB maximum INL, 1.00 LSB maximum DNL and 9.06 ENOB.partially_openopenPaolo Crovetti; Roberto Rubino; Francesco MusolinoCrovetti, PAOLO STEFANO; Rubino, Roberto; Musolino, Francesc

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion