Relative Stability of the Inner-Current Loop of Peak Current-Mode Controlled PWM DC-DC Converters in CCM

Current-mode control is a commonly adopted method of regulation for pulse-width modulated (PWM) dc-dc power converters in industry, but is not well understood. The advantages of current-mode control over the voltage-mode control include inherent overload and short circuit protection, faster response, line-noise rejection, and multiple converter paralleling. Current-mode controlled system consists of (1) an inner-current loop and (2) an outer-voltage loop, which sets the reference voltage to the inner loop. To ensure stable operation of the multi-loop converter, all the sequential loops in the circuit should be stable with sufficient degree of stability. The research in this dissertation is focused on the relative stability of the inner-current loop in peak current-mode (PCM) controlled PWM dc-dc converters operating in CCM. The operating principle of peak current-mode control is presented. The inner-current loop dynamics of a peak current-mode controlled dc-dc converter is investigated using perturbation theory. Considering its mixed-signal (analog and digital) behavior, the current loop is modeled using sample-and-hold theory. Taking the discrete nature of the inner-current loop into account, a closed-loop transfer function for the current loop is derived in z-domain and an equivalent-hold approximation is used to derive an approximate closed-loop transfer function in the continuous s-domain using modified Pad´e approximation. A general expression for the loop gain of the inner-loop, independent of the converter topology, is derived. Using the loop gain, a measure of relative stability of the inner loop is developed. Expressions for amount of slope compensation required at maximum duty cycle, for the inner loop to be marginally stable and to achieve a specified margin of stability, are derived. Also, expressions for maximum duty cycle at a given amount of slope compensation, for the inner loop to be marginally stable and to obtain a specified margin of stability, are derived. The control current expressions for the inner loop of peak current-mode controlled converters without and with slope compensation are derived. A procedure to design the inner-current loop is developed. Saber Sketch simulation and experimental results are presented to validate the presented theory. The dynamic behavior of the inner-current loop of peak current-mode controlled PWM dc-dc buck converter operating in CCM is analyzed. The critical path power stage transfer functions, the relevant inner-current loop transfer functions, and the control-to-output transfer function of peak current-mode controlled PWM dc-dc buck converter operating in CCM are derived. The presented model is validated using experimental Bode plots

Design and analysis of feedback controllers for a DC buck-boost converter

In Murdoch University, students majoring in Electrical Power Engineering have the opportunity to learn about the basics of power electronic systems. ENG349 Power Electronic Converters and Systems is a unit where students are exposed to a range of industrial electronics. The power pole board provided by the University of Minnesota is used for laboratory teaching on how DC converters operate [1, 2]. This thesis topic gives an opportunity for Electrical Power students to further expand their basic knowledge on power electronics. Additionally, Instrumentation and Control System Engineering students will have a better understanding of dynamic control systems, which are essential in designing and analysing feedback control on DC converters. Industrial computer systems students are able to design and implement external hardware to enhance power board components. Renewable Energy students will be interested in how DC converters are applied to renewable energy systems. This thesis provides project expansion for all types of electrical engineering majors taught at Murdoch University. The main focus of this thesis is to design and analyse different feedback controllers for the converter system. The literature review and steps into designing feedback controllers are adapted from Ned Mohan’s approach in designing feedback controllers for DC converters [3]. The results presented are based on the author’s knowledge learnt from Electrical Power and Instrumentation and Control Systems Engineering. Computer simulations from Pspice and MATLAB are used for testing the feedback responses of implementing different feedback compensators. The most difficult task in this thesis is to produce accurate results from the power pole board, especially with the peak current controller circuit. Although the simulated results are successful, it is hard to compare these to the experimental results due to the ways of how the power board components are connected. This thesis will further explain the process in exploring these feedback controllers

Analysis of a new family of DC-DC converters with input-parallel output-series structure

There is an increasing trend of development and installation of switching power supplies due to their highly efficient power conversion, fast power control and high quality power conditioning for applications such as renewable energy integration and energy storage management systems. In most of these applications, high voltage conversion ratio is required. However, basic switching converters have limited voltage conversion ratio. There has been much research into development of high gain power converters. While most of the reported topologies focus on high gain and high efficiency, in this thesis, the input and output ripple currents and reliability are also considered to derive a new converter structure suitable for high step-up voltage conversion applications. High ripple currents and voltages at the input and output of dc-dc converters are not desirable because they may affect the operation of the dc source or the load. A number of converters operating in an interleaved manner can reduce these ripples. This thesis proposes a dc/dc switching converter structure which is capable of reducing the ripple problem through interleaved action, in addition to high gain and high efficiency voltage conversion. The thesis analyses the proposed converter structure through a dual buck-boost converter topology. The structure allows different converter topologies and combinations of them for different applications to be configured. The study begins with a motivation and a literature review of dc/dc converters. The new family of high step-up converters is introduced with an interleaved buck-boost as an example, followed by small-signal analysis. Experimental verifications, conclusions and future work are discussed

Analysis of a new family of DC-DC converters with input-parallel output-series structure

There is an increasing trend of development and installation of switching power supplies due to their highly efficient power conversion, fast power control and high quality power conditioning for applications such as renewable energy integration and energy storage management systems. In most of these applications, high voltage conversion ratio is required. However, basic switching converters have limited voltage conversion ratio. There has been much research into development of high gain power converters. While most of the reported topologies focus on high gain and high efficiency, in this thesis, the input and output ripple currents and reliability are also considered to derive a new converter structure suitable for high step-up voltage conversion applications. High ripple currents and voltages at the input and output of dc-dc converters are not desirable because they may affect the operation of the dc source or the load. A number of converters operating in an interleaved manner can reduce these ripples. This thesis proposes a dc/dc switching converter structure which is capable of reducing the ripple problem through interleaved action, in addition to high gain and high efficiency voltage conversion. The thesis analyses the proposed converter structure through a dual buck-boost converter topology. The structure allows different converter topologies and combinations of them for different applications to be configured. The study begins with a motivation and a literature review of dc/dc converters. The new family of high step-up converters is introduced with an interleaved buck-boost as an example, followed by small-signal analysis. Experimental verifications, conclusions and future work are discussed

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

Low Voltage Regulator Modules and Single Stage Front-end Converters

Evolution in microprocessor technology poses new challenges for supplying power to these devices. To meet demands for faster and more efficient data processing, modem microprocessors are being designed with lower voltage implementations. More devices will be packed on a single processor chip and the processors will operate at higher frequencies, exceeding 1GHz. New high-performance microprocessors may require from 40 to 80 watts of power for the CPU alone. Load current must be supplied with up to 30A/µs slew rate while keeping the output voltage within tight regulation and response time tolerances. Therefore, special power supplies and Voltage Regulator Modules (VRMs) are needed to provide lower voltage with higher current and fast response. In the part one (chapter 2,3,4) of this dissertation, several low-voltage high-current VRM technologies are proposed for future generation microprocessors and ICs. The developed VRMs with these new technologies have advantages over conventional ones in terms of efficiency, transient response and cost. In most cases, the VRMs draw currents from DC bus for which front-end converters are used as a DC source. As the use of AC/DC frond-end converters continues to increase, more distorted mains current is drawn from the line, resulting in lower power factor and high total harmonic distortion. As a branch of active Power factor correction (PFC) techniques, the single-stage technique receives particular attention because of its low cost implementation. Moreover, with continuously demands for even higher power density, switching mode power supply operating at high-frequency is required because at high switching frequency, the size and weight of circuit components can be remarkably reduced. To boost the switching frequency, the soft-switching technique was introduced to alleviate the switching losses. The part two (chapter 5,6) of the dissertation presents several topologies for this front-end application. The design considerations, simulation results and experimental verification are discussed

High efficiency smart voltage regulating module for green mobile computing

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption