Arithmetic Operations in Multi-Valued Logic

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.Comment: 12 Pages, VLSICS Journal 201

Comparison of Binary and Multi-Level Logic Electronics for Embedded Systems

Embedded systems are dependent on low-power, miniaturized instrumentation. Comparator circuits are common elements in applications for digital threshold detection. A multi-level, memory-based logic approach is in development that offers potential benefits in power usage and size with respect to traditional binary logic systems. Basic 4-bit operations with CMOS gates and comparators are chosen to compare circuit implementations of binary structures and quaternary equivalents. Circuit layouts and functional operation are presented. In particular, power characteristics and transistor count are examined. The potential for improved embedded systems based on the multilevel, memory-based logic is discussed

Power Optimization of Combinational Quaternary Logic Circuits

Design of the binary logic circuits is restricted by the need of the interconnections. Interconnections increase delay, area and energy consumption in CMOS digital circuits. A possible solution could be here at by using a bigger set of signals over the same chip area. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of necessary interconnections. In this paper we design various combinational circuits using quaternary logic. Various combinational circuit such as multi valued logic full adder using unique encoding technique, quaternary encoder and quaternary multiplexer. This design is target to reduce the transistor used to implement the circuit and dropping the power dissipation. Power optimization is achieved using MTCMOS technique. Simulation has been done in Tanner 13 EDA tool on BSIM3 180 nm CMOS Technology. DOI: 10.17762/ijritcc2321-8169.15026

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs

Design of High Performance Quaternary Adders

Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents two types of multiple-valued full adder circuits, implemented in Multiple-Valued voltage-Mode Logic (MV-VML). First type is designed using one hot encoding and barrel shifter. Second full adder circuit is designed by converting the quaternary logic in to unique code, which enables to implement circuit with reduced hard ware. Sum and carry are processed in two separate blocks, controlled by code generator unit. The design is targeted for the 0.18 μm CMOS technology and verification of the design is done through Synopsis HSPICE and COSMOSCOPE Tools. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less

Review On High Performance Quaternary Arithmetic and Logical Unit in Standard CMOS

Arithmetic circuits play an important role in computational circuits. Multiple Valued Logic (MVL) provides higher density per integrated circuit area compared to traditional two valued binary logic. Quaternary (Four-valued) logic also provides easy interfacing to binary logic because radix 4(22) allows for the use of simple encoding/decoding circuits. The functional completeness is proved by a set of fundamental quaternary cells and the collection of cells based on the Supplementary Symmetrical Logic Circuit Structure (SUSLOC). Cells are designed, simulated, and used to build several quaternary fixed-point arithmetic circuits such as adders, multipliers etc. These SUSLOC circuit cells are validated using SPICE models and the arithmetic architectures are validated using System Verilog models for functional correctness. Quaternary (radix-4) dual operand encoding principles are applied to optimize power and performance of adder circuits using standard CMOS gates technologies

Design of Quaternary Logic Carry Look-Ahead Adder

In today's state-of-the-art VLSI technology, binary number system has been the choice for designing digital subsystems. Although technology development has made down scaling of devices possible, which in turn has resulted in a remarkable increase in density and functionality of VLSI systems, there are also significant drawbacks associated to the conventional binary number based system implementations. As the number of devices in VLSI circuits increases to billion of transistors in a chip area of , interconnection between the active devices both on chip and outside of a chip becomes considerably complicated. In a typical VLSI chip, about 70 percent of the chip area is occupied by interconnections whereas just 10 percent of the chip area is devoted to the devices and the remaining 20 percent is used for insulation. mm2 In this situation, multiple valued logics have attracted a considerable attention of researchers as a solution to overcome the above mentioned problem. Since fewer digits are required to represent a number in higher radices than in the binary number system, multiple valued logic circuits have the potential to minimize the number of interconnections. This thesis presents voltage-mode quaternary (4-valued) logic carry lookahead adder design using Silicon-On-Insulator (SOI) MOSFETs. The choice of adder subsystem is made because addition operation is the most frequently used operation in a general purpose system and in application specific processors. Further more, the other operations like subtraction, multiplication and division are based on addition operation of the arithmetic unit. In this study, an efficient logic to realize 4-valued logic addition operation is proposed. The presented method is in conjunction with binary logic concepts and is easily developed for look-ahead logic. Following the proposed method has resulted in logic circuits with shorter gate depth and faster speed of operation as compared to what the other researchers have proposed. To meet the design requirements of the proposed low-voltage low-power circuits, multiple threshold voltage SOI MOSFETs are used. This choice is made because of their capability to operate at low power supply voltages and their ability to remain at the adjusted threshold voltages while presenting better subthreshold characteristics compared to the bulk MOSFETs. The proposed half and full adder blocks are divided into a few subblocks which could be considered as primitive gates. Transistor-Resistor Logic is used to implement each of them. Spice simulations have been performed on the proposed logic subblocks and their transient behaviors have been studied. Finally, the propagation delay, power consumption and overall performance of the proposed circuits are compared with other adder circuits proposed by other researchers. The presented adder circuits in this work have shown up to 58% reduction in critical propagation delay and 20% less power dissipation resulting in 64% reduction in power-delay product in comparison with other reported work. When compared to the binary logic carry look-ahead adder using the same technology (SOI), 54.39% improvement in power dissipation was achieved