Overexpressing temperature-sensitive dynamin decelerates phototransduction and bundles microtubules in drosophila photoreceptors

shibire(ts1), a temperature-sensitive mutation of the Drosophila gene encoding a Dynamin orthologue, blocks vesicle endocytosis and thus synaptic transmission, at elevated, or restrictive temperatures. By targeted Gal4 expression, UAS-shibire(ts1) has been used to dissect neuronal circuits. We investigated the effects of UAS-shibire(ts1) overexpression in Drosophila photoreceptors at permissive (19 degrees C) and restrictive (31 degrees C) temperatures. At 19 degrees C, overexpression of UAS-shi(ts1) causes decelerated phototransduction and reduced neurotransmitter release. This phenotype is exacerbated with dark adaptation, age and in white mutants. Photoreceptors overexpressing UAS-shibire(ts1) contain terminals with widespread vacuolated mitochondria, reduced numbers of vesicles and bundled microtubules. Immuno-electron microscopy reveals that the latter are dynamin coated. Further, the microtubule phenotype is not restricted to photoreceptors, as UAS-shibire(ts1) overexpression in lamina cells also bundles microtubules. We conclude that dynamin has multiple functions that are interrupted by UAS-shibire(ts1) overexpression in Drosophila photoreceptors, destabilizing their neural communication irreversibly at previously reported permissive temperatures

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.Comment: To appear at the DSN 2020 conferenc