Kupari-tina mikroliitosten karakterisointimenetelmät

The microelectronics industry constantly aspires to shrink the device features. At the package level, this implies a decrease in the interconnect size leading to small volume interconnections that are commonly called micro-connects. Smaller material volumes may give rise to new reliability challenges, such as open circuits, due to Kirkendall voiding. The root cause(s) for Kirkendall voiding is not yet clear and the methods for characterization are still varied. This thesis reviews techniques to characterize the microstructure and impurities in Cu-Sn micro-connects. The evaluated techniques are Auger Electron Spectroscopy (AES), Electron Energy Loss Spectroscopy (EELS), Energy-Dispersive X-Ray Spectroscopy (EDX), X-Ray Spectroscopy (XPS), Secondary Ion Mass Spectrometry (SIMS), Rutherford Backscattering Spectrometry (RBS), Elastic Recoil Detection Analysis (EELS), Transmission Electron Microscopy (TEM), Focused Ion Beam (FIB), and Scanning Acoustic Microscopy (SAM). From the reviewed techniques, EDX, FIB, SAM, and TEM are used in the experimental section. For the first time, impurities are measured directly inside Kirkendall voids. It was discovered that the Kirkendall voids in annealed Cu-Sn samples contained a significant amount of chlorine and oxygen. The ASTM grain size counting method was applied to FIB-polished samples. It was observed that the grain size did not increase by annealing at 150 ◦C. Furthermore, for the first time, GHz-SAM was used to characterize Kirkendall voids. The technique is promising but it is still affected by the low lateral resolution.Mikroelektroniikkateollisuus pyrkii jatkuvasti pienentämään laitekokoa. Paketointitasolla tämä tarkoittaa sitä, että sirujen välisten liitosten kokoluokka on siirtymässä kohti mikroliitoksia, jotka saattavat aiheuttaa uusia luotettavuusongelmia. Kirkendall-aukot ovat yksi syy kyseisiin luotettavuusongelmiin ja aukkojen alkuperä on vielä tuntematon. Sen lisäksi, mikroliitosten ja Kirkendall aukkojen karakterisointiin käytetään toisistaan poikkeavia menetelmiä eikä sopivista metodeista ole vielä yhteisymmärrystä. Tämä diplomityö tarkastelee kupari-tina mikroliitoksien mikrorakenteen ja epäpuhtauksien analysointiin käytettyjä menetelmiä. Tarkasteltavat menetelmät ovat Auger elektronispektroskopia (AES), epäelastinen elektronisironta (EELS), energiadispersiivinen röntgenspektroskopia (EDX), röntgenfotoelektronispektroskopia (XPS), sekundääri ionimassaspektroskopia (SIMS), Rutherford-takaisinsirontaspektroskopia (RBS), rekyylispektrometria (ERDA), läpäisyelektronimikroskopia (TEM), keskitetty ionisuihku (FIB) ja akustinen mikroskopia (SAM). Esitellyistä menetelmistä kokeellisessa osiossa käytettiin EDX:ää, FIB:ä, SAM:a ja (S)TEM:ä. Tässä diplomityössä on mitattu ensimmäistä kertaa epäpuhtauksia Kirkendall-aukkojen sisältä. Mittauksista saatiin selville, että hehkutettujen kupari-tina -näytteiden Kirkendall-aukot sisälsivät huomattavan määrän happea ja klooria. Raekokoa tarkasteltiin kiillottamalla näytteet FIB:llä ja soveltamalla ASTM:n raekoko -standardia. Työssä huomattiin, että raekoko ei kasvanut, jos näytteitä hehkutettiin 150 ◦C lämpötilassa. Tämä on myös ensimmäinen kerta, kun GHzSAM:a on käytetty Kirkendall-aukkojen tutkimiseen. Tulokset olivat lupaavia, mutta menetelmän alhainen sivuttaissuuntainen resoluutio on vielä rajoittava tekijä

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

異種ダイレット積層を用いたフレキシブルハイブリッドデバイスの集積技術に関する研究

Tohoku University福島誉史課

Convolutional neural network (CNNs) based image diagnosis for failure analysis of power devices

An image diagnosis by deep learning was applied to failure analysis of power devices. A series of images during a process to failure by power cycling test was used for this method. The images were obtained by a scanning acoustic microscopy of our real-time monitoring system. An image classifier was designed based on a convolutional neural network (CNNs). A developed classifier successfully diagnosed input image into a normal device and an abnormal device. The accuracy of classification was improved by introducing a pre-training and an overlapping pooling into the system. A technique to extract a feature related a failure is essential for the failure analysis based on the real-time monitoring and the deep learning is one likely candidate for it

Numerical Study For Acoustic Micro-Imaging Of Three Dimensional Microelectronic Packages

Complex structures and multiple interfaces of modern microelectronic packages complicate the interpretation of acoustic data. This study has four novel contributions. 1) Contributions to the finite element method. 2) Novel approaches to reduce computational cost. 3) New post processing technologies to interpret the simulation data. 4) Formation of theoretical guidance for acoustic image interpretation. The impact of simulation resolution on the numerical dispersion error and the exploration of quadrilateral infinite boundaries make up the first part of this thesis's contributions. The former focuses on establishing the convergence score of varying resolution densities in the time and spatial domain against a very high fidelity numerical solution. The latter evaluates the configuration of quadrilateral infinite boundaries in comparison against traditional circular infinite boundaries and quadrilateral Perfectly Matched Layers. The second part of this study features the modelling of a flip chip with a 140µm solder bump assembly, which is implemented with a 230MHz virtual raster scanning transducer with a spot size of 17µm. The Virtual Transducer was designed to reduce the total numerical elements from hundreds of millions to hundreds of thousands. Thirdly, two techniques are invented to analyze and evaluate simulated acoustic data: 1) The C-Line plot is a 2D max plot of specific gate interfaces that allows quantitative characterization of acoustic phenomena. 2) The Acoustic Propagation Map, contour maps an overall summary of intra sample wave propagation across the time domain in one image. Lastly, combining all the developments. The physical mechanics of edge effects was studied and verified against experimental data. A direct relationship between transducer spot size and edge effect severity was established. At regions with edge effect, the acoustic pulse interfacing with the solder bump edge is scattered mainly along the horizontal axis. The edge effect did not manifest in solder bump models without Under Bump Metallization (UBM). Measurements found acoustic penetration improvements of up to 44% with the removal of (UBM). Other acoustic mechanisms were also discovered and explored. Defect detection mechanism was investigated by modelling crack propagation in the solder bump assembly. Gradual progression of the crack was found have a predictable influence on the edge effect profile. By exploiting this feature, the progress of crack propagation from experimental data can be interpreted by evaluating the C-Scan image

Novel development of distributed manufacturing monitoring systems to support high cost and complexity manufacturing

In the current manufacturing environment, characterized by diverse change sources (e.g. economical, technological, political, social) and integrated supply chains, success demands close cooperation and coordination between stakeholders and agility. Tools and systems based on software agents, intelligent products and virtual enterprises have been developed to achieve such demands but either because of: (i) focus on a single application; (ii) focus on a single product; (iii) separation between the product and its information; or (iv) focus on a single system characteristic (e.g. hardware, software, architecture, requirements) their use has been limited to trial or academic scenarios. In this thesis a reusable distributed manufacturing monitoring system for harsh environments, capable of addressing traceability and controllability requirements within stakeholders and across high cost and complexity supply chains is presented. [Continues.

A Review and Analysis of Automatic Optical Inspection and Quality Monitoring Methods in Electronics Industry

Electronics industry is one of the fastest evolving, innovative, and most competitive industries. In order to meet the high consumption demands on electronics components, quality standards of the products must be well-maintained. Automatic optical inspection (AOI) is one of the non-destructive techniques used in quality inspection of various products. This technique is considered robust and can replace human inspectors who are subjected to dull and fatigue in performing inspection tasks. A fully automated optical inspection system consists of hardware and software setups. Hardware setup include image sensor and illumination settings and is responsible to acquire the digital image, while the software part implements an inspection algorithm to extract the features of the acquired images and classify them into defected and non-defected based on the user requirements. A sorting mechanism can be used to separate the defective products from the good ones. This article provides a comprehensive review of the various AOI systems used in electronics, micro-electronics, and opto-electronics industries. In this review the defects of the commonly inspected electronic components, such as semiconductor wafers, flat panel displays, printed circuit boards and light emitting diodes, are first explained. Hardware setups used in acquiring images are then discussed in terms of the camera and lighting source selection and configuration. The inspection algorithms used for detecting the defects in the electronic components are discussed in terms of the preprocessing, feature extraction and classification tools used for this purpose. Recent articles that used deep learning algorithms are also reviewed. The article concludes by highlighting the current trends and possible future research directions.Framework of the IQONIC Project; European Union’s Horizon 2020 Research and Innovation Program

PROGNOSTIC MODELING FOR RELIABILITY PREDICTIONS OF POWER ELECTRONIC DEVICES

The applications of semiconductor power electronic devices, including power and RF devices, in industry have stringent requirements on their reliability. Power devices are subject to various types of failure mechanisms under various stressors. Prognostics and health management (PHM) allows detecting signs of failures, providing warnings of failures in advance, and performing condition-based maintenance. There is a pressing need to develop a robust prognostic model to detect anomalous behavior and predict the lifetime of devices that can be applicable to different types of power transistors. In the present dissertation, a comprehensive prognostic model for remaining useful life (RUL) prediction of semiconductor power electronic devices is developed. The model consists of an anomaly detection module and a RUL prediction module including a non-linear system process model describing the evolution of parametric degradation, and a measurement model. The anomaly detection module uses principal component analysis (PCA) for dimensionality reduction and feature extraction, as well as k-means clustering to establish baseline clusters in the feature space. The novel singular-value-weighted distance (SVWD) is developed as the distance measure in the feature space, based on which Fisher criterion (FC) is used for anomaly probability calculation. The system process model incorporates variables concerning loading conditions and physics-of-failure of devices, and uses particle filter (PF) approach for process model training and RUL prediction. For PF methodology, a novel resampling technique, called MHA-replacement resampling, is developed to solve the particle degeneracy in classic PF techniques and sample impoverishment in traditional resampling techniques. The developed prognostic model is first implemented on IGBT modules for validation. It was reported that the module package of power transistors was susceptible to various types of fatigue-related failure modes due to coefficient of thermal expansion (CTE) mismatches under temperature/power cycles introducing thermomechanical stresses. The physics-of-failure "driving variable" is derived from Paris equation. The model is validated on several time-series IGBT module degradation data under power cycles from literature sources, based on SIR particle filter for RUL prediction with good accuracy. Then the model is implemented on GaN HEMTs, a representative of wide-bandgap semiconductor power devices. GaN HEMTs are susceptible to degradation mechanisms such as ohmic contact inter-diffusion that leads to voiding in the field plate at high temperature under RF accelerated life tests (ALTs). The time-series data of the physics-of-failure "driving variable" is obtained from diffusion computation in Mathematica with the temperature prole coming from COMSOL thermal simulation. The RUL prediction results based on SIR lter are also satisfactory for GaN HEMTs. For each type of device, the new resampling technique is validated through performance benchmarking against state-of-the-art resampling techniques. Another reliability threat for GaN HEMTs, especially in aerospace and nuclear applications, is the degradation due to radiation effect on the device performance. Gamma radiation has been found to lead to generation of defects in AlGaN/GaN layers, which form complexes acting as carrier traps, thus reducing carrier density and current. EPC GaN HEMTs are irradiated under a wide range of Gamma ray doses and critical DC characteristics are recorded before and after radiation to quantify their shifts during the irradiation. Future work needed to allow implementation of the developed prognostic model for RUL estimation is proposed

Understanding, Modeling and Predicting Hidden Solder Joint Shape Using Active Thermography

Characterizing hidden solder joint shapes is essential for electronics reliability. Active thermography is a methodology to identify hidden defects inside an object by means of surface abnormal thermal response after applying a heat flux. This research focused on understanding, modeling, and predicting hidden solder joint shapes. An experimental model based on active thermography was used to understand how the solder joint shapes affect the surface thermal response (grand average cooling rate or GACR) of electronic multi cover PCB assemblies. Next, a numerical model simulated the active thermography technique, investigated technique limitations and extended technique applicability to characterize hidden solder joint shapes. Finally, a prediction model determined the optimum active thermography conditions to achieve an adequate hidden solder joint shape characterization. The experimental model determined that solder joint shape plays a higher role for visible than for hidden solder joints in the GACR; however, a MANOVA analysis proved that hidden solder joint shapes are significantly different when describe by the GACR. An artificial neural networks classifier proved that the distances between experimental solder joint shapes GACR must be larger than 0.12 to achieve 85% of accuracy classifying. The numerical model achieved minimum agreements of 95.27% and 86.64%, with the experimental temperatures and GACRs at the center of the PCB assembly top cover, respectively. The parametric analysis proved that solder joint shape discriminability is directly proportional to heat flux, but inversely proportional to covers number and heating time. In addition, the parametric analysis determined that active thermography is limited to five covers to discriminate among hidden solder joint shapes. A prediction model was developed based on the parametric numerical data to determine the appropriate amount of energy to discriminate among solder joint shapes for up to five covers. The degree of agreement between the prediction model and the experimental model was determined to be within a 90.6% for one and two covers. The prediction model is limited to only three solder joints, but these research principles can be applied to generate more realistic prediction models for large scale electronic assemblies like ball grid array assemblies having as much as 600 solder joints

VeloElectric: Creating a Device that Harvests Energy From Bicycles

Long distance mountain bikers, bike-packers, and many bikers in developing countries rely on electrical devices for safety and communication. These specific groups of people operate in areas with little to no electricity, and often times have no power to sustain their devices. The purpose of this Cal Poly senior project, VeloElectric, was to design, build, and test a kinetic energy harvester for bicycles that can be used to charge common mobile devices via USB. This senior project team created a device that attaches directly to a bicycle and uses vibrations to generate energy, which in turn powers a variety of portable devices. The final product will be used by Professor Lynne Slivovsky on a bike ride from Canada to Mexico. This document contains information on the entire project during the 2014-2015 school year. The “Background” section summarizes research and case studies including dynamo chargers and an electromagnetic induction charger called the nPower PEG. The Pedl team used this information to generate initial design ideas such as using piezoelectrics and other kinetic energy harvesting devices. This research was also used to gain a better understanding of the current state of art for this type of product. The end of the background section provides details of the project management plan that was used through the course of the projects focusing heavily on the tasks completed during Spring quarter. Following the “Background” section is an explanation of the development of conceptual designs that lead to the final product. Conceptual designs included decision matrices to decide on a 3D printed exterior casing, Velcro straps for attachment, electromagnetic induction for energy generation, and a battery for energy storage. Diagrams, models and pictures of the end product are displayed and analyzed in the “Description of Final Design” section. This section shows the exterior casing that was created to house the inner casing, battery, and printed circuit board. The “Product Realization” section focuses on how a lathe was used to create the final inner casing, 3D printing for the exterior casing and inner casing caps, and simple soldering for the electrical components. The section also explains how the final prototype cost the team about $200, but through mass production could be lowered to about$45. The “Design Verification” section discusses how the final iteration was tested and includes test descriptions and photos while documenting the results of these tests. Example tests include weight, bike transfer time, USB compatibility, and vibrational tolerance. The document concludes by discussing the progress that was made on the project throughout the year and the recommendations that the design team has for possible future teams assigned to this task