Evaluation of three coding schemes designed for improved data communication

Three coding schemes designed for improved data communication are evaluated. Four block codes are evaluated relative to a quality function, which is a function of both the amount of data rejected and the error rate. The Viterbi maximum likelihood decoding algorithm as a decoding procedure is reviewed. This evaluation is obtained by simulating the system on a digital computer. Short constraint length rate 1/2 quick-look codes are studied, and their performance is compared to general nonsystematic codes

Iterative decoding for error resilient wireless data transmission

Both turbo codes and LDPC codes form two new classes of codes that offer energy efficiencies close to theoretical limit predicted by Claude Shannon. The features of turbo codes include parallel code catenation, recursive convolutional encoders, punctured convolutional codes and an associated decoding algorithm. The features of LDPC codes include code construction, encoding algorithm, and an associated decoding algorithm. This dissertation specifically describes the process of encoding and decoding for both turbo and LDPC codes and demonstrates the performance comparison between theses two codes in terms of some performance factors. In addition, a more general discussion of iterative decoding is presented. One significant contribution of this dissertation is a study of some major performance factors that intensely contribute in the performance of both turbo codes and LDPC codes. These include Bit Error Rate, latency, code rate and computational resources. Simulation results show the performance of turbo codes and LDPC codes under different performance factors

A hardware spinal decoder

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel alpha-beta incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters. We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.Irwin Mark Jacobs and Joan Klein Jacobs Presidential FellowshipIntel Corporation (Fellowship)Claude E. Shannon Research Assistantshi

Cascaded tree codes

Cascaded tree codes for sequential decoding in presence of nois

Physical layer secrecy channel coding

Wireless communications is expanding and becoming an indispensable part of our daily life. However, due to its channel open nature, it is more vulnerable to attacks, such as eavesdropping and jamming which jeopardize the confidentiality of wireless data, compared to its counter-part, wireline communications. Security in wireless communication is thus a very important factor that should be perfected to accommodate the rapid growth of wireless communication today. Motivated by information theoretic secrecy definitions, we adopt a simple way to define the secrecy of a system by looking at its Bit-Error-Rate (BER) curves, the correlation of error vectors and Log Likelihood Ratios (LLRs) of the decoded information bits. The information bit errors and LLRs of a physical layer secure system should be uncorrelated and the BER curve should have an acceptable sharp transition from high to low BERs at prescribed signal to noise ratio (SNR) thresholds. We study catastrophic codes and Serial Concatenated Convolutional Codes (SCCC) as two candidates. For the former, we provide both detailed analytical and simulation results, to demonstrate how we can change the encoding parameters to make the resulting BER curves have the intended properties. For SCCC, we study two options. One is having a catastrophic code as an inner code. The other is to use regular SCCC. Several approaches are proposed to change the shape of the resulting BER curves. In addition, the correlation present in their information bit errors and LLRs are investigated to see how it can be used to detect or even correct errors. We find that regular SCCC codes have strong correlation in their error vectors which is captured by the associated LLRs. In low SNR regions, eavesdropper can easily make reliable decisions on which packets to drop based on LLRs, which thus undermines the security of the main channel data. On the other hand, by selecting proper outer codes, SCCC with catastrophic encoder does not have such a weakness. We conclude that Catastrophic convolutional codes, as well as serial concatenated catastrophic codes have desired properties. Therefore, they can be considered promising approaches to achieving practical secrecy in wireless systems

Hardware implementation of a pipelined turbo decoder

Turbo codes have been widely studied since they were first proposed in 1993 by Berrou, Glavieux, and Thitimajshima in "Near Shannon Limit error-correcting coding and decoding: Turbo-codes" [1]. They have the advantage of providing a low bit error rate (BER) in decoding, and outperform linear block and convolutional codes in low signal-to-noise-ratio (SNR) environments. The decoding performance of turbo codes can be very close to the Shannon Limit, about 0.7decibel (dB). It is determined by the architectures of the constituent encoders and interleaver, but is bounded in high SNRs by an error floor. Turbo codes are widely used in communications. We explore the codeword weight spectrum properties that contribute to their excellent performance. Furthermore, the decoding performance is analyzed and compared with the free distance asymptotic performance. A 16-state turbo decoder is implemented using VHSIC Hardware Description Language (VHDL) and then mapped onto a field-programmable gate array (FPGA) board. The hardware implementations are compared with the software simulations to verify the decoding correctness. A pipelined architecture is then implemented which significantly reduces the decoding latency. -- Keywords: turbo codes; decoding performance; Monte Carlo simulations; FPGA implementatio

New VLSI design of a MAP/BCJR decoder.

Any communication channel suffers from different kinds of noises. By employing forward error correction (FEC) techniques, the reliability of the communication channel can be increased. One of the emerging FEC methods is turbo coding (iterative coding), which employs soft input soft output (SISO) decoding algorithms like maximum a posteriori (MAP) algorithm in its constituent decoders. In this thesis we introduce a design with lower complexity and less than 0.1dB performance loss compare to the best performance observed in Max-Log-MAP algorithm. A parallel and pipeline design of a MAP decoder suitable for ASIC (Application Specific Integrated Circuits) is used to increase the throughput of the chip. The branch metric calculation unit is studied in detail and a new design with lower complexity is proposed. The design is also flexible to communication block sizes, which makes it ideal for variable frame length communication systems. A new even-spaced quantization technique for the proposed MAP decoder is utilized. Normalization techniques are studied and a suitable technique for the Max-Log-MAP decoder is explained. The decoder chip is synthesized and implemented in a 0.18 mum six-layer metal CMOS technology. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .S23. Source: Masters Abstracts International, Volume: 43-05, page: 1783. Adviser: Majid Ahmadi. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Challenges and Some New Directions in Channel Coding

Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, nonbinary LDPC codes, and polar coding.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/JCN.2015.00006

TCM Decoding Using Neural Networks

This paper presents a neural decoder for trellis coded modulation (TCM) schemes. Decoding is performed with Radial Basis Function Networks and Multi-Layer Perceptrons. The neural decoder effectively implements an adaptive Viterbi algorithm for TCM which learns communication channel imperfections. The implementation and performance of the neural decoder for trellis encoded 16-QAM with amplitude imbalance are analyzed

Cascaded tree codes.

Also issued as a Ph.D. thesis in the Dept. of Electrical Engineering, 1970