On-the-fly reconfigurable logic

©2005 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only. Copyright 2004 Society of Photo-Optical Instrumentation Engineers. This paper was published in Smart Structures, Devices, and Systems II, edited by Said F. Al-Sarawi, Proceedings of SPIE Vol. 5649 and is made available as an electronic reprint with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and sequential logic. In this paper we investigate various RC technologies and discuss possible methods to optimise their power, speed and area. To address the drawbacks of existing RC technologies we propose a generic architecture we call "OFRL" (On-the-Fly Reconfigurable Logic). Our objective is to provide a low power, high speed platform for reconfigurable circuit and dynamically reconfigurable logic applications that use fewer transistors than existing technologies.Kamal Rajagopalan, Braden Phillips, and Derek Abbot

Study on multi-objective optimization of circuit design by evolutionary computation technologies

制度:新 ; 報告番号:甲3364号 ; 学位の種類:博士(工学) ; 授与年月日:2011/4/25 ; 早大学位記番号:新568

Using Partial Reconfiguration for SoC Design and Implementation

Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the pape