806 research outputs found
Developing the knowledge-based human resources that support the implementation of the National Dual Training System (NDTS): evaluation of TVET teacher's competency at MARA Training Institutions
Development in the world of technical and vocational education and training (TVET)
on an ongoing basis is a challenge to the profession of the TVET-teachers to
maintain their performance. The ability of teachers to identify the competencies
required by their profession is very critical to enable them to make improvements in
teaching and learning. For a broader perspective the competency needs of the labour
market have to be matched by those developed within the vocational learning
processes. Consequently, this study has focused on developing and validating the
new empirical based TVET-teacher competency profile and evaluating teacher’s
competency. This study combines both quantitative and qualitative research
methodology that was designed to answer all the research questions. The new
empirical based competency profile development and TVET-teacher evaluation was
based upon an instructional design model. In addition, a modified Delphi technique
has also been adopted throughout the process. Initially, 98 elements of competencies
were listed by expert panel and rated by TVET institutions as important. Then,
analysis using manual and statistical procedure found that 112 elements of
competencies have emerged from seventeen (17) clusters of competencies. Prior to
that, using the preliminary TVET-teacher competency profile, the level of TVETteacher
competencies was found to be Proficient and the finding of 112 elements of
competencies with 17 clusters was finally used to develop the new empirical based
competency profile for MARA TVET-teacher. Mean score analysis of teacher
competencies found that there were gaps in teacher competencies between MARA
institutions (IKM) and other TVET institutions, where MARA-teacher was
significantly better than other TVET teacher. ANOVA and t-test analysis showed
that there were significant differences between teacher competencies among all
TVET institutions in Malaysia. On the other hand, the study showed that teacher’s
age, grade and year of experience are not significant predictors for TVET-teacher
competency. In the context of mastering the competency, the study also found that
three competencies are classified as most difficult or challenging, twelve
competencies are classified as should be improved, and eight competencies are
classified as needed to be trained. Lastly, to make NDTS implementation a reality
for MARA the new empirical based competency profile and the framework for
career development and training pathway were established. This Framework would
serve as a significant tool to develop the knowledge based human resources needed.
This will ensure that TVET-teachers at MARA are trained to be knowledgeable,
competent, and professional and become a pedagogical leader on an ongoing basis
towards a world class TVET-education system
Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors
Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance
Logic Gates and Ring Oscillators Based on Ambipolar Nanocrystalline-Silicon TFTs
Nanocrystalline silicon (nc-Si) thin film transistors (TFTs) are well suited for circuit applications that require moderate device performance and low-temperature CMOS-compatible processing below 250°C. Basic logic gate circuits fabricated using ambipolar nc-Si TFTs alone are presented and shown to operate with correct outputs at frequencies of up to 100 kHz. Ring oscillators consisting of nc-Si TFT-based inverters are also shown to operate at above 20 kHz with a supply voltage of 5 V, corresponding to a propagation delay of 5 V for several hours
Novel a‐Si:H TFT pixel circuit for electrically stable top‐anode light‐emitting AMOLEDs
Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/92120/1/1.2770853.pd
RFID Logic circuit with oxide TFTs modeled by genetic algorithms
Nos últimos anos, a necessidade por técnicas de identificação com velocidades de leitura superiores e maior flexibilidade relativamente à memória e programabilidade, levaram ao desenvolvimento de tecnologias de identificação de rádio frequência (RFID). Esta tecnologia já provou o seu valor no futuro da Internet das coisas (IoT), ao permitir a possibilidade de marcar qualquer tipo de produto facilmente e com baixo custo por etiqueta, enquanto possibilita a conexão deste tipo de etiquetas com smartphones para aumentar a ligação entre os dispositivos RFID e a vida quotidiana. Além disto, a introdução de transístores de filme fino (TFT) de óxidos amorfos em circuitos RFID, abre um novo mundo de aplicações, visto que este tipo de dispositivos permite o uso de substratos transparentes e/ou flexíveis, devido à possibilidade de usar baixas temperaturas durante o processo de fabrico para este tipo de transístores.
Neste trabalho, foi usado o Modelo a-Si Nível 61 com a ajuda de algoritmos genéticos para criar modelos de transístores de a-IGZO produzidos com um dielétrico de porta depositado por métodos de solução usando spin-coating. Com estes modelos, foi dimensionado um circuito digital de RFID, usando uma topologia em que o transístor de carga está em configuração de díodo, para ler uma memória ROM de 16-bit e posteriormente codificar o sinal através de uma codificação de Manchester com uma taxa de transferência de 14 kbit/s.
Este tipo de circuitos utilizando substratos transparentes e/ou flexíveis pode possibilitar no futuro a criação de embalagens inteligentes para bens domésticos e a posterior integração numa configuração de frigoríficos inteligentes. Isto significa que poderá ser possível uma pessoa ser avisada quando é necessário comprar um produto ou quando ultrapassa o prazo de validade.In recent years, the need for identification techniques, with faster reading speed and more flexibility regarding memory and programmability, led to the development of Radio Frequency Identification technologies. This technology has already proven to be essential in the future of Internet-of-Things, by allowing the possibility of tagging any type of product easily and at low cost per tag, while also allowing the interface of these tags, with common smartphones to increase the connectivity of RFID devices in daily life. Furthermore, the introduction of amorphous IGZO thin film transistors in RFID circuits, opens a new world of applications since this type of devices allows the use of transparent and/or flexible substrates, due to the low temperatures required during the fabrication process.
In this work, it was used the a-Si Level 61 TFT Model together with genetic algorithms, to model a-IGZO transistors produced, with a gate dielectric deposited by a solution method using spin coating. With these models, it was designed an RFID logic circuit, which employs diode connected structures, to read a 16-bit Read Only Memory and encode the signal using a Manchester encoding technique, with a data rate of 14 kbit/s.
These types of circuits using transparent and/or flexible substrates could allow, in the future, the creation of smart packaging for regular house goods and integrate it in a smart fridge configuration. Meaning that, it could be possible to a person either to be advised when to buy a certain item or when it reaches the expiration date
Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.
The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated
On the Reversible Effects of Bias-Stress Applied to Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors
The role of amorphous IGZO (Indium Gallium Zinc Oxide) in Thin Film Transistors (TFT) has found its application in emerging display technologies such as active matrix liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) due to factors such as high mobility 10-20 cm2/(V.s), low subthreshold swing (~120mV/dec), overall material stability and ease of fabrication. However, prolonged application of gate bias on the TFT results in deterioration of I-V characteristics such as sub-threshold distortion and a distinct shift in threshold voltage. Both positive-bias and negative-bias affects have been investigated. In most cases positive-stress was found to have negligible influence on device characteristics, however a stress induced trap state was evident in certain cases. Negative stress demonstrated a pronounced influence by donor like interface traps, with significant transfer characteristics shift that was reversible over a period of time at room temperature. It was also found that the reversible mechanism to pre-stress conditions was accelerated when samples were subjected to cryogenic temperature (77 K). To improve device performance BG devices were subjected to extended anneals and encapsulated with ALD alumina. These devices were found to have excellent resistance to bias stress. Double gate devices that were subjected to extended anneals and alumina capping revealed similar results with better electrostatics compared to BG devices. The cause and effect of bias stress and its reversible mechanisms on IGZO TFTs has been studied and explained with supporting models
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