140,927 research outputs found

    Very Large-Scale Integrated Processor

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    Demonstration of Tunable Optical Notch Filter Using 1-D Opto-VLSI Processor

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    An opto-very-large-scale-integrated (opto-VLSI)-based tunable optical filter structure is demonstrated. Filter tunability is achieved by reconfiguring the holographic diffraction grating of an opto-VLSI processor, allowing virtually any type of filter response to be synthesized. A proof-of-concept tunable notch filter with wavelength span of 7 nm is experimentally verifie

    Test aspects of the JPL Viterbi decoder

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    The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults

    100 kW Nested Hall Thruster System Development

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    Large scale cargo transportation to support human missions to the Moon and Mars will require very high power Solar Electric Propulsion (SEP) systems operating between 200 and 400 kW. Aerojet Rocketdyne's NextSTEP program is developing and demonstrating a 100 kW EP system, the XR-100, using a Nested Hall Thruster (NHT) designed for powers up to 200 kW, a modular power processor and a modular flow controller. The three year program objective is to operate the integrated EP system continuously at 100 kW for 100 h, advancing this very high power Electric Propulsion (EP) system to Technology Readiness Level (TRL) 5. With our University of Michigan, Jet Propulsion Laboratory and NASA Glenn Research Center teammates, Aerojet Rocketdyne has completed the initial phase of the program, including operating the thruster at up to 30 kW to validate the thermal models and developing and operating multiple power processor modules in the required seriesparallel configuration. The current phase includes completing a TRL 4 integrated system test at reduced power to validate all system operating phases. Design upgrades to demonstrate the TRL 5 capabilities are underway. This paper will present the high power XR-100 capabilities, overall program and design approach and the latest test results for the 100 kW EP system demonstration program

    Hybrid VLSI/QCA Architecture for Computing FFTs

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    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes

    Opto-VLSI-Based reconfigurable free space optical interconnects architecture

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    This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms

    Systolic and Hyper-Systolic Algorithms for the Gravitational N-Body Problem, with an Application to Brownian Motion

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    A systolic algorithm rhythmically computes and passes data through a network of processors. We investigate the performance of systolic algorithms for implementing the gravitational N-body problem on distributed-memory computers. Systolic algorithms minimize memory requirements by distributing the particles between processors. We show that the performance of systolic routines can be greatly enhanced by the use of non-blocking communication, which allows particle coordinates to be communicated at the same time that force calculations are being carried out. Hyper-systolic algorithms reduce the communication complexity at the expense of increased memory demands. As an example of an application requiring large N, we use the systolic algorithm to carry out direct-summation simulations using 10^6 particles of the Brownian motion of the supermassive black hole at the center of the Milky Way galaxy. We predict a 3D random velocity of 0.4 km/s for the black hole.Comment: 33 pages, 10 postscript figure

    Memory and information processing in neuromorphic systems

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    A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system
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