64 research outputs found

    Parallel Architectures for Planetary Exploration Requirements (PAPER)

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    The Parallel Architectures for Planetary Exploration Requirements (PAPER) project is essentially research oriented towards technology insertion issues for NASA's unmanned planetary probes. It was initiated to complement and augment the long-term efforts for space exploration with particular reference to NASA/LaRC's (NASA Langley Research Center) research needs for planetary exploration missions of the mid and late 1990s. The requirements for space missions as given in the somewhat dated Advanced Information Processing Systems (AIPS) requirements document are contrasted with the new requirements from JPL/Caltech involving sensor data capture and scene analysis. It is shown that more stringent requirements have arisen as a result of technological advancements. Two possible architectures, the AIPS Proof of Concept (POC) configuration and the MAX Fault-tolerant dataflow multiprocessor, were evaluated. The main observation was that the AIPS design is biased towards fault tolerance and may not be an ideal architecture for planetary and deep space probes due to high cost and complexity. The MAX concepts appears to be a promising candidate, except that more detailed information is required. The feasibility for adding neural computation capability to this architecture needs to be studied. Key impact issues for architectural design of computing systems meant for planetary missions were also identified

    Faulty-Tolerant Algorithm for Mapping a Complete Binary Tree in an IEH

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    [[abstract]]Different parallel architectures may require different algorithms to make the existent algorithms on one architecture be easily transformed to or implemented on another architecture. This paper proposes a novel algorithm for embedding complete binary trees in a faulty Incrementally Extensible Hypercube (IEH). Furthermore, to obtain the replaceable node of the faulty node, 2-expansion is permitted such that up to (n+1) faults can be tolerated with dilation 3, congestion 1 and load 1. The presented embedding methods are optimized mainly for balancing the processor loads, while minimizing dilation and congestion as far as possible. According to the result, we can map the parallel algorithms developed by the structure of complete binary tree in an IEH. These methods of reconfiguring enable extremely high-speed parallel computation.[[notice]]補正完畢[[journaltype]]國外[[incitationindex]]EI[[booktype]]紙本[[countrycodes]]GR

    Simulation of Meshes in a Faulty Supercube with Unbounded Expansion

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    [[abstract]]Reconfiguring meshes in a faulty Supercube is investigated in the paper. The result can readily be used in the optimal embedding of a mesh (or a torus) of processors in a faulty Supercube with unbounded expansion. There are embedding algorithms proposed in this paper. These embedding algorithms show a mesh with any number of nodes can be embedded into a faulty Supercube with load 1, congestion 1, and dilation 3 such that O(n2-w2) faults can be tolerated, where n is the dimension of the Supercube and 2w is the number of nodes of the mesh. The meshes and hypercubes are widely used interconnection architectures in parallel computing, grid computing, sensor network, and cloud computing. In addition, the Supercubes are superior to hypercube in terms of embedding a mesh and torus under faults. Therefore, we can easily port the parallel or distributed algorithms developed for these structuring of mesh and torus to the Supercube.[[notice]]補正完畢[[journaltype]]國外[[incitationindex]]EI[[ispeerreviewed]]Y[[booktype]]紙本[[countrycodes]]KO

    Distributed Fault-Tolerant Embeddings of Rings in Incrementally Extensible Hypercubes with Unbounded Expansion

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    [[abstract]]The Incrementally Extensible Hypercube (IEH) is a generalization of interconnection network that is derived from the hypercube. Unlike the hypercube, the IEH can be constructed for any number of nodes. That is, the IEH is incrementally expandable. In this paper, the problem of embedding and reconfiguring ring structures is considered in an IEH with faulty nodes. There are a novel embedding algorithm proposed in this paper. The embedding algorithm enables us to obtain the good embedding of a ring into a faulty IEH with unbounded expansion, and such the result can be tolerated up to O(n*log2m ) faults with congestion 1, load 1, and dilation 4. The presented embedding methods are optimized mainly for balancing the processor loads, while minimizing dilation and congestion as far as possible.[[notice]]補正完畢[[journaltype]]國際[[incitationindex]]EI[[ispeerreviewed]]Y[[booktype]]紙本[[countrycodes]]TW

    Lower bounds for dilation, wirelength, and edge congestion of embedding graphs into hypercubes

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    Interconnection networks provide an effective mechanism for exchanging data between processors in a parallel computing system. One of the most efficient interconnection networks is the hypercube due to its structural regularity, potential for parallel computation of various algorithms, and the high degree of fault tolerance. Thus it becomes the first choice of topological structure of parallel processing and computing systems. In this paper, lower bounds for the dilation, wirelength, and edge congestion of an embedding of a graph into a hypercube are proved. Two of these bounds are expressed in terms of the bisection width. Applying these results, the dilation and wirelength of embedding of certain complete multipartite graphs, folded hypercubes, wheels, and specific Cartesian products are computed
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