Aligning tool set metrics for operation in a Multi Technology High Mix Low Volume manufacturing environment

Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; in conjunction with the Leaders for Manufacturing Program at MIT, 2005.Includes bibliographical references (p. 81).Ireland Fab Operations (IFO) is transitioning and leading the way within Intel to Multi- Technology High Mix Low Volume (MT-HMLV) manufacturing. To avoid errors in estimating metrics, specific capacity tool set metrics for this manufacturing environment now need to be considered. Approximations for high volume manufacturing may be far enough from MT-HMLV realities that company revenue is affected by making delivery commitments that can not be met. The Intel Model of Record (MOR) which is used to determine the number of each tool set needed to produce a given volume of product does not consider MT-HMLV realities. Things such as product change-overs, cross qualified tools, and smaller than 'normal' lot sizes can create chaos on the manufacturing floor that has not been traditionally accounted for.by Alyson B. Naughton.S.M.M.B.A

Using simulation to analyze operational policies in a combined development and production fabrication facility

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; and, (S.M.)--Massachusetts Institute of Technology, Sloan School of Management, 1998.Includes bibliographical references (leaf 68).by Celia A. Dieterich.S.M

Development and application of low Reynolds number turbulence models for air-cooled electronics

Semiconductors are at the heart of electronic devices such as computers, mobile phones, avionics systems, telecommunication racks, etc. Power dissipation from semiconductor devices is continuing to increase due to the growth in the number of transistors on the silicon chip as predicted by Moore's Law. Thermal management techniques, used to dissipate this power, are becoming more and more challenging to design. Air cooling of electronic components is the preferred method for many designs where the air flow is characterised as being in the laminar-to-turbulent transitional region. Over the last fifteen years there has been a dramatic take-up of Computational Fluid Dynamics (CFD) technology in the electronics industry to simulate the airflow and temperatures in electronic systems. These codes solve the Reynolds Averaged Navier-Stokes (RANS) equations for momentum and turbulence. RANS models are popular as they are much quicker to solve than time-dependent models such as Large Eddy Simulation (LES) or Direct Numerical Simulation (DNS). At present the majority of thermal design engineers use the standard k-e model which is a high Reynolds number model. This is because there is limited knowledge on the benefit of using low Reynolds number models in the electronics cooling industry. This Ph.D. investigated and developed low Reynolds number models for use in electronics cooling CFD calculations. Nine turbulence models were implemented and validated in the in-house CFD code PHYSICA. This includes three zero-equation, two single equation, and four zonal models. All of these models are described in the public literature except the following two models which were developed in this study: AUTO_CAP: This zero-equation model automates the existing LVEL_CAP model available within the commercial CFD code FLOTHERM. ke I kl: This zonal model uses a new approach to blend the k — l model used at the wall with the k-e model used to predict the bulk airflow. Validation of these turbulence models was undertaken on eight different test cases. This included the detailed experimental work undertaken by Meinders. Results show that the ke I kl model provides the most accurate flow predictions. For prediction of temperature there was no clear favourite. This was probably due to the use of the universal log-law function in this study. A generalised wall function may be more appropriate. Results from this research have been disseminated through a total of nine peer-reviewed conference and journal publications, evidence of the interest the topic of this investigation generates amongst electronic packaging engineers

Formal connectivity verification of clock and reset signals in ultra-low-power SoC designs

Abstract. This thesis investigates the usage of formal connectivity verification on clock and reset signal connectivity in ultra-low-power SoC designs. The origin of power consumption in CMOS circuits is explained, and the conflict between dynamic and static power on system parameter level is introduced. Common power reduction techniques are introduced and explained in some detail. Overview of functional verification and its role in the design flow is presented. The main classification of functional verification into logic simulation and formal verification is discussed, and details of both are explained and compared. Challenges rising from low power design methodologies are introduced. Detailed view of connectivity and integration in SoC designs is provided, and a specified method of verifying connectivity is introduced in the form of formal connectivity verification. The practical part of the thesis starts with an explanation of the verification goal and requirements for achieving it. Structure of the design environment used in the verification task is explained, and the different stages that the verification was conducted on. Creation of used connectivity properties and the used process flow for the chosen software tool is presented. The process of confirming falsified properties as design bugs is introduced. The results of the verification task are presented, providing the total target amount for each verification stage, as well as the found bugs. The found bugs and their circumstances are explained. Comparison is made between the conventional method of verifying connectivity and the investigated formal method. Results show a great decrease in overall work effort, resourcing and time spent on the connectivity verification.Formaali liitettävyysverifiointi kello- ja reset-signaaleille ultra-matalan tehonkulutuksen järjestelmäpiireissä. Tiivistelmä. Tämä diplomityö tutkii formaalin liitettävyysverifionnin käyttöä kello- ja reset-signaalien yhteyksille ultra-matalan tehonkulutuksen järjestelmäpiireissä. Tehonkulutuksen lähteet CMOS piireissä selitetään, ja esitetään konflikti dynaamisen ja staattisen tehonkulutuksen välillä systeemin parametritasolla. Tavanomaisia tehonkulutusta vähentäviä tekniikoita esitellään ja selitetään jossain määrin. Funktionaalisen verifioinnin yleiskatsaus ja asema suunnitteluvuossa esitellään. Funktionaalisen verifioinnin pääjaottelua logiikkasimulaatioon ja formaaliin verifiointiin käsitellään, ja molempien yksityiskohtia selitetään ja vertaillaan. Matalan tehonkulutuksen metodologioiden aiheuttamat ongelmat esitetään. Yksityiskohtainen kuvaus liitettävyydestä ja integroinnista järjestelmäpiireissä selitetään, ja eritelty metodi liitettävyyden verifioimiselle esitellään formaalin liitettävyysverifionnin muodossa. Käytännön osuus diplomityöstä alkaa verifoinnin tavoitteen ja vaatimusten esittelemisellä. Käytetyn mallin rakenne ja verifiointitehtävä selitetään, sekä eri tasot joilla verifiointi suoritettiin. Liitettävyys-ominaisuuksien luominen, sekä käytetty prosessivuo valitulle työkalulle esitetään. Vääriksi todistettujen ominaisuuksien varmistaminen suunnitteluvirheiksi esitellään. Tulokset verifointitehtävästä esitellään, käsitellen verifioinnin kohteiden kokonaista lukumäärää molemmilla verifiointitasoilla, sekä niistä löydettyjen virheiden määrää. Löydetyt suunnitteluvirheet ja niiden seikkaperät selitetään. Vertailua tehdään perinteisen liitettävyyden verifionnin metodin ja tutkitun formaalin metodin välillä. Tulokset osoittavat suuren säästön kokonaisessa työmäärässä, resurssoinnissa sekä liitettävyyden verifiointiin kulutetussa ajassa

Synthesis and Study of Verdazyl Stable Free Radical Substituted Oligothiophenes for Magnetoresistive and Spintronic Properties

Interest in spin polarizing materials and their application in electronic devices in the field of spintronics has been steadily growing in recent years. The development of wholly organic spin polarizing materials has been of particular interest due to the material flexibility, solution processing, synthetic modifiability, and longer spin lifetimes of organics compared to inorganic analogs. One class of organic compounds with significant room for exploration is polyconjugated π systems coupled with stable radicals. We have explored the synthesis of oligothiophenes substituted with verdazyl stable free radicals with differing thiophene chain lengths, through a series of halogenation, borylation, and palladium catalyzed Suzuki-Miyarua coupling reactions. The characterization methods employed include IR, NMR, UV-Vis, ESR, GC/LC-MS, and X-ray crystallography. We have successfully synthesized two novel bisverdazyls with conjugated oligomer spacers and analyzed the magnetism, electrochemical redox potentials, crystal structure, and molecular packing of the aforementioned diradicals. We hope to build on this work by analyzing the bisverdazyls for their magnetoresistance, conductivity, and spin polarization properties. Furthermore, we also plan to synthesize more efficient bisverdazyl conjugated spacers utilizing EDOT units, which promise improved conductivity and spin propagation

Reusable modelling and simulation of flexible manufacturing for next generation semiconductor manufacturing facilities

Automated material handling systems (AMHS) in 300 mm semiconductor manufacturing facilities may need to evolve faster than expected considering the high performance demands on these facilities. Reusable simulation models are needed to cope with the demands of this dynamic environment and to deliver answers to the industry much faster. One vision for intrabay AMHS is to link a small group of intrabay AMHS systems, within a full manufacturing facility, together using what is called a Merge/Diverge link. This promises better operational performance of the AMHS when compared to operating two dedicated AMHS systems, one for interbay transport and the other for intrabay handling. A generic tool for modelling and simulation of an intrabay AMHS (GTIA-M&S) is built, which utilises a library of different blocks representing the different components of any intrabay material handling system. GTIA-M&S provides a means for rapid building and analysis of an intrabay AMHS under different operating conditions. The ease of use of the tool means that inexpert users have the ability to generate good models. Models developed by the tool can be executed with the merge/diverge capability enabled or disabled to provide comparable solutions to production demands and to compare these two different configurations of intrabay AMHS using a single simulation model. Finally, results from simulation experiments on a model developed using the tool were very informative in that they include useful decision making data, which can now be used to further enhance and update the design and operational characteristics of the intrabay AMHS