391 research outputs found

    Bidirectional Electric Vehicles Service Integration in Smart Power Grid with Renewable Energy Resources

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    As electric vehicles (EVs) become more popular, the utility companies are forced to increase power generations in the grid. However, these EVs are capable of providing power to the grid to deliver different grid ancillary services in a concept known as vehicle-to-grid (V2G) and grid-to-vehicle (G2V), in which the EV can serve as a load or source at the same time. These services can provide more benefits when they are integrated with Photovoltaic (PV) generation. The proper modeling, design and control for the power conversion systems that provide the optimum integration among the EVs, PV generations and grid are investigated in this thesis. The coupling between the PV generation and integration bus is accomplished through a unidirectional converter. Precise dynamic and small-signal models for the grid-connected PV power system are developed and utilized to predict the system’s performance during the different operating conditions. An advanced intelligent maximum power point tracker based on fuzzy logic control is developed and designed using a mix between the analytical model and genetic algorithm optimization. The EV is connected to the integration bus through a bidirectional inductive wireless power transfer system (BIWPTS), which allows the EV to be charged and discharged wirelessly during the long-term parking, transient stops and movement. Accurate analytical and physics-based models for the BIWPTS are developed and utilized to forecast its performance, and novel practical limitations for the active and reactive power-flow during G2V and V2G operations are stated. A comparative and assessment analysis for the different compensation topologies in the symmetrical BIWPTS was performed based on analytical, simulation and experimental data. Also, a magnetic design optimization for the double-D power pad based on finite-element analysis is achieved. The nonlinearities in the BIWPTS due to the magnetic material and the high-frequency components are investigated rely on a physics-based co-simulation platform. Also, a novel two-layer predictive power-flow controller that manages the bidirectional power-flow between the EV and grid is developed, implemented and tested. In addition, the feasibility of deploying the quasi-dynamic wireless power transfer technology on the road to charge the EV during the transient stops at the traffic signals is proven

    Thermal Investigations Of Flip Chip Microelectronic Package With Non-Uniform Power Distribution [TK7874. G614 2004 f rb] [Microfiche 7607].

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    Arah aliran pempakejan sistem-sistem dan subsistem mikroelektronik adalah kearah pengurangan saiz dan peningkatan prestasi, di mana kedua-duanya menyumbang kepada peningkatan kadar penjanaan haba. The trend in packaging microelectronic systems and subsystems has been to reduce size and increase performance, both of which contribute to increase heat generation

    Design of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey

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    Includes bibliographical references (leaves 101-105).This thesis describes the design and implementation of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey (HSHS). The Hubble Space Hydrogen Survey was initiated in an effort to build a low-cost cylindrical radio telescope for an all sky redshift survey with the observational goal to produce a 3-dimensional mapping of the bulk Hubble Sphere using Hydrogen 21cm emissions. This dissertation ï¬ rst investigates the system design to see how each of the user speciï¬ cations set by the planning team could be achieved in terms of design decisions, component selection and schematic capture. The final design. AstroGIG, satisï¬ es the user speciï¬ cations by capturing data up to a full power bandwidth of 1.7GHz with an instantaneous bandwidth of ≤ 250MHz white maximizing the dynamic range. AstroGIG buffers, processes, stores and ï¬ nally transmits the data through a 4-lane PCI-Express interface to a standard PC where the majority of the processing is performed. The system implementation is then described where issues relating to the process of transforming schematics into a physical PCB, and HSHS integration are discussed. The design is veriï¬ ed through Hyperlynx simulations to give a high degree of certainty that physical implementation and production would be successful. Results from tests on the actual hardware characterizing the overall system performance are presented. Conclusions are drawn based on these results and suggestions for future work and design improvements are recommended

    LHCb base-line level-0 trigger 3D-flow implementation

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    The LHCb Level-0 trigger implementation with the 3D-Flow system offers full programmability, allowing it to adapt to unexpected operating conditions and enabling new, unpredicted physics. The implementation is described in detail and refers to components and technology available today. The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on the replication of a single type of circuit of 100 k gates, which communicates in six directions: bi-directional with North, East, West, and South neighbors, unidirectional from Top to Bottom, the system offers full programmability, modularity, ease of expansion and adaptation to the latest technology. A complete study of its applicability to the LHCb calorimeter triggers is presented. Full description of the input data handling, either in digital or mixed digital-analog form, of the data processing, and the transmission of results to the global level-0 trigger decision unit are provided. Any level-0 trigger algorithm (2*2, 3*3, 4*4, etc.) with up to 20 steps, can be implemented with zero dead-time, while sustaining input data rate (up to 32-bit per input channel, per bunch crossing) at 40 MHz. For each step, each 3D-Flow processor can execute up to 26 operations, inclusive of compare, ranging, finding local maxima, and efficient data exchange with neighboring channels. (One-to-one correspondence between input channel and trigger tower.) Populated with only two main types of components, front-end FPGAs and 3D-Flow processors, a single type of board, it is shown how the whole Level-0 calorimeter trigger can be accommodated into six crates (9U), each containing 16 identical boards. All 3D-Flow inter-chip Bottom to Top ports connection are all contained on the board (data are multiplexed 2:1, PCB traces are shorter than 6 cm); all 3D-flow inter-chip North, East, West, and South ports connections, between boards and crates, are multiplexed (8+2):1 and are shorter than 1.5 m. Full implementation of a 3D-Flow system, for the most complex trigger algorithm, requires 320 cables to north and south crates and 40 cables to east and west crates (Cable cost=$2 each). For applications requiring a simpler real-time algorithm (e.g., requiring less than 20 steps, which is equivalent to 10 layers of 3D-Flow- processors), then the number of connections for the inter-boards (North and South), and inter-crates (East and West) will also be reduced to the number of layers used by the simpler algorithm, thus not requiring to install all cables (e.g., applications requiring only nine layers of 3D-Flow processors will save 32 cables to the North, 32 to the South, four to the East, and four to the West crates). Details are also given on timing and synchronization issues, ASIC design verification, real-time performance monitoring and design (software and hardware) development tools. (37 refs)

    Heterogeneous 2.5D integration on through silicon interposer

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    © 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

    The design and implementation of a flexible manufacturing system for a surface mounting production line

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    A project report submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in partial fulfillment of the requirements for the degree of Master of Science in Engineering.The viability of introducing a Surface Mount production line is chiefly determined by the reliability characteristics of the components being used. Surface Mount Technology (SMT) is entirely new and although related to traditional through-hole processes, requires different components, assembly techniques and design methods. The purpose of the literature survey is primarily to determine whether surface mount components meet today's industrial requirements with respect to their manufacturing reliability and availability. A brief review of the evolution of SMT is also presented. This study finds that the implementation of SMT should be given highest priority by manufacturing companies in order to maintain their share of the marketplace. Surface Mount Technology embodies a totally new automated circuit assembly process, using a new generation of electronic comporents: surface mounted devices (SMDs). Smaller than conventional components, SMDs are placed onto the surface of the substrate. From this, the fundamental difference between SMD assembly and convencional through-hole component assembly arises; SMD component positioning is relative, not absolute. When a through-hole component is inserted into a pcb, either the leads go through the hales or they don't. An SMD, however, is placed onto the substrate surface, it's position only relative to the solder lands, and placement accuracy is therefore influenced by variations in the substrate track pattern, component size, and placement machine accuracy. Other factors influence the layout of SMD substrates. For example, will the board be a mixed-print ( a combination of through-hole components and SMDs) or an all-SMD design? Will SMDs be placed on one side of the substrate or both? And there are process considerations like what type of machine will place the components and how will they be soldered? This project describes in detail the processes involved in setting up an SMT facility. A simulation program was developed to verify the viability of these processes. The simulation program was also applied to an existing SMT facility and together with developed optimization software, attempted to identify and resolve some of the major problems. All this was achieved, and the extent to which simulation could be used as an efficient production tool, was highlighted.AC201

    Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

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    This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100fsrms) for high-performance ADCs. The key ideas of the design methodology are: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18μm and 1.2V 90nm). Post-layout simulation results for a case of study with typical jitter of 68fs for a 1.8V 80dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.Gobierno de España TEC2015-68448-REuropean Space Agency 4000108445-13-NL-R

    MakerFluidics: low cost microfluidics for synthetic biology

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    Recent advancements in multilayer, multicellular, genetic logic circuits often rely on manual intervention throughout the computation cycle and orthogonal signals for each chemical “wire”. These constraints can prevent genetic circuits from scaling. Microfluidic devices can be used to mitigate these constraints. However, continuous-flow microfluidics are largely designed through artisanal processes involving hand-drawing features and accomplishing design rule checks visually: processes that are also inextensible. Additionally, continuous-flow microfluidic routing is only a consideration during chip design and, once built, the routing structure becomes “frozen in silicon,” or for many microfluidic chips “frozen in polydimethylsiloxane (PDMS)”; any changes to fluid routing often require an entirely new device and control infrastructure. The cost of fabricating and controlling a new device is high in terms of time and money; attempts to reduce one cost measure are, generally, paid through increases in the other. This work has three main thrusts: to create a microfluidic fabrication framework, called MakerFluidics, that lowers the barrier to entry for designing and fabricating microfluidics in a manner amenable to automation; to prove this methodology can design, fabricate, and control complex and novel microfluidic devices; and to demonstrate the methodology can be used to solve biologically-relevant problems. Utilizing accessible technologies, rapid prototyping, and scalable design practices, the MakerFluidics framework has demonstrated its ability to design, fabricate and control novel, complex and scalable microfludic devices. This was proven through the development of a reconfigurable, continuous-flow routing fabric driven by a modular, scalable primitive called a transposer. In addition to creating complex microfluidic networks, MakerFluidics was deployed in support of cutting-edge, application-focused research at the Charles Stark Draper Laboratory. Informed by a design of experiments approach using the parametric rapid prototyping capabilities made possible by MakerFluidics, a plastic blood--bacteria separation device was optimized, demonstrating that the new device geometry can separate bacteria from blood while operating at 275% greater flow rate as well as reduce the power requirement by 82% for equivalent separation performance when compared to the state of the art. Ultimately, MakerFluidics demonstrated the ability to design, fabricate, and control complex and practical microfluidic devices while lowering the barrier to entry to continuous-flow microfluidics, thus democratizing cutting edge technology beyond a handful of well-resourced and specialized labs
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