Polarization Imaging Sensors in Advanced Feature CMOS Technologies

The scaling of CMOS technology, as predicted by Moore\u27s law, has allowed for realization of high resolution imaging sensors and for the emergence of multi-mega-pixel imagers. Designing imaging sensors in advanced feature technologies poses many challenges especially since transistor models do not accurately portray their performance in these technologies. Furthermore, transistors fabricated in advanced feature technologies operate in a non-conventional mode known as velocity saturation. Traditionally, analog designers have been discouraged from designing circuits in this mode of operation due to the low gain properties in single transistor amplifiers. Nevertheless, velocity saturation will become even more prominent mode of operation as transistors continue to shrink and warrants careful design of circuits that can exploit this mode of operation. In this research endeavor, I have utilized velocity saturation mode of operation in order to realize low noise imaging sensors. These imaging sensors incorporate low noise analog circuits at the focal plane in order to improve the signal to noise ratio and are fabricated in 0.18 micron technology. Furthermore, I have explored nanofabrication techniques for realizing metallic nanowires acting as polarization filters. These nanoscopic metallic wires are deposited on the surface of the CMOS imaging sensor in order to add polarization sensitivity to the CMOS imaging sensor. This hybrid sensor will serve as a test bed for exploring the next generation of low noise and highly sensitive polarization imaging sensors

A 12.8 k current-mode velocity-saturation ISFET array for on-chip real-time DNA detection

This paper presents a large-scale CMOS chemical-sensing array operating in current mode for real-time ion imaging and detection of DNA amplification. We show that the current-mode operation of ion-sensitive field-effect transistors in velocity saturation devices can be exploited to achieve an almost perfect linearity in their input-output characteristics (pH-current), which are aligned with the continuous scaling trend of transistors in CMOS. The array is implemented in a 0.35-m process and includes 12.8 k sensors configured in a 2T per pixel topology. We characterize the array by taking into account nonideal effects observed with floating gate devices, such as increased pixel mismatch due to trapped charge and attenuation of the input signal due to the passivation capacitance, and show that the selected biasing regime allows for a sufficiently large linear range that ensures a linear pH to current despite the increased mismatch. The proposed system achieves a sensitivity of 1.03 A/pH with a pH resolution of 0.101 pH and is suitable for the real-time detection of the NDM carbapenemase gene in E. Coli using a loop-mediated isothermal amplification

Radiation Effects in Pinned Photodiode CMOS Image Sensors: Pixel Performance Degradation Due to Total Ionizing Dose

Several Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are designed, manufactured, characterized and exposed biased to ionizing radiation up to 10 kGy(SiO2 ). In addition to the usually reported dark current increase and quantum efficiency drop at short wavelengths, several original radiation effects are shown: an increase of the pinning voltage, a decrease of the buried photodiode full well capacity, a large change in charge transfer efficiency, the creation of a large number of Total Ionizing Dose (TID) induced Dark Current Random Telegraph Signal (DC-RTS) centers active in the photodiode (even when the Transfer Gate (TG) is accumulated) and the complete depletion of the Pre-Metal Dielectric (PMD) interface at the highest TID leading to a large dark current and the loss of control of the TG on the dark current. The proposed mechanisms at the origin of these degradations are discussed. It is also demonstrated that biasing (i.e., operating) the PPD CIS during irradiation does not enhance the degradations compared to sensors grounded during irradiation