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Designing an efficient test pattern generator using input reduction with linear operations
Advances in fabrication technology have resulted in more complicated systems, being used in ever increasing numbers of applications. The large increase in transistor counts versus the number of pins on the chip has made VLSI testing much harder than ever before. Denser integrated circuits chips increase the required test cases enormously for comprehensive testing of a chip. This results in expensive test cost and long test time. In this thesis, an improved method for on-chip test pattern generation is proposed. It generates a complete test set more efficiently by using input reduction with linear operations. Input reduction for pseudo-exhaustive test pattern generation based on compatible and inverse-compatible relationships between inputs has been proposed in the past. This work extends the concept by using linear combinations of inputs to generate other inputs as a means for further input reduction. Results are presented showing the improvements that can be obtained.Electrical and Computer Engineerin
Testing a Quantum Computer
The problem of quantum test is formally addressed. The presented method
attempts the quantum role of classical test generation and test set reduction
methods known from standard binary and analog circuits. QuFault, the authors
software package generates test plans for arbitrary quantum circuits using the
very efficient simulator QuIDDPro[1]. The quantum fault table is introduced and
mathematically formalized, and the test generation method explained.Comment: 15 pages, 17 equations, 27 tables, 8 figure
Fault Models for Quantum Mechanical Switching Networks
The difference between faults and errors is that, unlike faults, errors can
be corrected using control codes. In classical test and verification one
develops a test set separating a correct circuit from a circuit containing any
considered fault. Classical faults are modelled at the logical level by fault
models that act on classical states. The stuck fault model, thought of as a
lead connected to a power rail or to a ground, is most typically considered. A
classical test set complete for the stuck fault model propagates both binary
basis states, 0 and 1, through all nodes in a network and is known to detect
many physical faults. A classical test set complete for the stuck fault model
allows all circuit nodes to be completely tested and verifies the function of
many gates. It is natural to ask if one may adapt any of the known classical
methods to test quantum circuits. Of course, classical fault models do not
capture all the logical failures found in quantum circuits. The first obstacle
faced when using methods from classical test is developing a set of realistic
quantum-logical fault models. Developing fault models to abstract the test
problem away from the device level motivated our study. Several results are
established. First, we describe typical modes of failure present in the
physical design of quantum circuits. From this we develop fault models for
quantum binary circuits that enable testing at the logical level. The
application of these fault models is shown by adapting the classical test set
generation technique known as constructing a fault table to generate quantum
test sets. A test set developed using this method is shown to detect each of
the considered faults.Comment: (almost) Forgotten rewrite from 200
Proof that akers' algorithm for locally exhaustive testing gives minimum test sets of combinational circuits with up to four outputs
In this paper, we prove that Akers' test generation algorithm for the locally exhaustive testing gives a minimum test set (MLTS) for every combinational circuit (CUT) with up to four outputs. That is, we clarify that Akers' test pattern generator can generate an MLTS for such CUT</p
Test aspects of the JPL Viterbi decoder
The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults
Techniques for the Synthesis of Reversible Toffoli Networks
This paper presents novel techniques for the synthesis of reversible networks
of Toffoli gates, as well as improvements to previous methods. Gate count and
technology oriented cost metrics are used. Our synthesis techniques are
independent of the cost metrics. Two new iterative synthesis procedure
employing Reed-Muller spectra are introduced and shown to complement earlier
synthesis approaches. The template simplification suggested in earlier work is
enhanced through introduction of a faster and more efficient template
application algorithm, updated (shorter) classification of the templates, and
presentation of the new templates of sizes 7 and 9. A novel ``resynthesis''
approach is introduced wherein a sequence of gates is chosen from a network,
and the reversible specification it realizes is resynthesized as an independent
problem in hopes of reducing the network cost. Empirical results are presented
to show that the methods are effective both in terms of the realization of all
3x3 reversible functions and larger reversible benchmark specifications.Comment: 20 pages, 5 figure
NEW METHODS FOR PSEUDOEXHAUSTIVE TESTING
Pseudoexhaustive testing of combinational circuits has become of great importance
recently. These methods are keeping most of the benefits of the classical exhaustive testing which
check every combination of the input signals, but they need a considerably shorter sequence of
test patterns. In this paper we give a survey of pseudoexhaustive testing. Two new code
construction methods are presented: a systematic procedure to generate an effective exhaustive
code for every two dimensional subspace of the inputs; and an extension of the codes from the k
dimensional space to k+1. The efficiency of the new methods is compared to the ones described
in the literature
Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits
The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours
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