6 GHz RF CMOS Active Inductor Band Pass Filter Design and Process Variation Detection

A 90nm CMOS active inductor band pass filter with automatic peak detection is demonstrated in this thesis. The active inductor band pass filter has a better performance than the passive band pass filter in on-chip circuit design, due to small area, larger gain and tunable frequency. However, process variation makes the active inductor band pass filter hard to be used widely in many applications. To settle this issue, an automatic voltage peak detector is introduced to detect the process variation direction and hope to be used to control the active inductor band pass filter center frequency and gain. The designed active filter shows center frequency of 6GHz and quality factor (Q) of 31.9. To drive the peak detector, two analog buffers are designed with f-dB over 6GHz, and one has 0dB gain at low frequency region, another one would emphasize 0dB gain on 6GHz. The voltage peak detector can detect the AC input amplitude range from 0.06V to 0.6 and produce a linear output DC voltage of 77.97mV to 726.65mV

Challenges and Opportunities for Multi-functional Oxide Thin Films for Voltage Tunable Radio Frequency/Microwave Components

There has been significant progress on the fundamental science and technological applications of complex oxides and multiferroics. Among complex oxide thin films, barium strontium titanate (BST) has become the material of choice for room-temperature-based voltage-tunable dielectric thin films, due to its large dielectric tunability and low microwave loss at room temperature. BST thin film varactor technology based reconfigurable radio frequency (RF)/microwave components have been demonstrated with the potential to lower the size, weight, and power needs of a future generation of communication and radar systems. Low-power multiferroic devices have also been recently demonstrated. Strong magneto-electric coupling has also been demonstrated in different multiferroic heterostructures, which show giant voltage control of the ferromagnetic resonance frequency of more than two octaves. This manuscript reviews recent advances in the processing, and application development for the complex oxides and multiferroics, with the focus on voltage tunable RF/microwave components. The over-arching goal of this review is to provide a synopsis of the current state-of the-art of complex oxide and multiferroic thin film materials and devices, identify technical issues and technical challenges that need to be overcome for successful insertion of the technology for both military and commercial applications, and provide mitigation strategies to address these technical challenges

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

From RF-Microsystem Technology to RF-Nanotechnology

The RF microsystem technology is believed to introduce a paradigm switch in the wireless revolution. Although only few companies are to date doing successful business with RF-MEMS, and on a case-by-case basis, important issues need yet to be addressed in order to maximize yield and performance stability and hence, outperform alternative competitive technologies (e.g. ferroelectric, SoS, SOI,…). Namely the behavior instability associated to: 1) internal stresses of the free standing thin layers (metal and/or dielectric) and 2) the mechanical contact degradation, be it ohmic or capacitive, which may occur due to low forces, on small areas, and while handling severe current densities.The investigation and understanding of these complex scenario, has been the core of theoretical and experimental investigations carried out in the framework of the research activity that will be presented here. The reported results encompass activities which go from coupled physics (multiphysics) modeling, to the development of experimental platforms intended to tackles the underlying physics of failure. Several original findings on RF-MEMS reliability in particular with respect to the major failure mechanisms such as dielectric charging, metal contact degradation and thermal induced phenomena have been obtained. The original use of advanced experimental setup (surface scanning microscopy, light interferometer profilometry) has allowed the definition of innovative methodology capable to isolate and separately tackle the different degradation phenomena under arbitrary working conditions. This has finally permitted on the one hand to shed some light on possible optimization (e.g. packaging) conditions, and on the other to explore the limits of microsystem technology down to the nanoscale. At nanoscale indeed many phenomena take place and can be exploited to either enhance conventional functionalities and performances (e.g. miniaturization, speed or frequency) or introduce new ones (e.g. ballistic transport). At nanoscale, moreover, many phenomena exhibit their most interesting properties in the RF spectrum (e.g. micromechanical resonances). Owing to the fact that today’s minimum manufacturable features have sizes comparable with the fundamental technological limits (e.g. surface roughness, metal grain size, …), the next generation of smart systems requires a switching paradigm on how new miniaturized components are conceived and fabricated. In fact endowed by superior electrical and mechanical performances, novel nanostructured materials (e.g. carbon based, as carbon nanotube (CNT) and graphene) may provide an answer to this endeavor. Extensively studied in the DC and in the optical range, the studies engaged in LAAS have been among the first to target microwave and millimiterwave transport properties in carbon-based material paving the way toward RF nanodevices. Preliminary modeling study performed on original test structures have highlighted the possibility to implement novel functionalities such as the coupling between the electromagnetic (RF) and microelectromechanical energy in vibrating CNT (toward the nanoradio) or the high speed detection based on ballistic transport in graphene three-terminal junction (TTJ). At the same time these study have contributed to identify the several challenges still laying ahead such as the development of adequate design and modeling tools (ballistic/diffusive, multiphysics and large scale factor) and practical implementation issues such as the effects of material quality and graphene-metal contact on the electrical transport. These subjects are the focus of presently on-going and future research activities and may represent a cornerstone of future wireless applications from microwave up to the THz range

Biomedical Engineering

Biomedical engineering is currently relatively wide scientific area which has been constantly bringing innovations with an objective to support and improve all areas of medicine such as therapy, diagnostics and rehabilitation. It holds a strong position also in natural and biological sciences. In the terms of application, biomedical engineering is present at almost all technical universities where some of them are targeted for the research and development in this area. The presented book brings chosen outputs and results of research and development tasks, often supported by important world or European framework programs or grant agencies. The knowledge and findings from the area of biomaterials, bioelectronics, bioinformatics, biomedical devices and tools or computer support in the processes of diagnostics and therapy are defined in a way that they bring both basic information to a reader and also specific outputs with a possible further use in research and development

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies

Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)

Adaptive Integrated Circuit Design for Variation Resilience and Security

The past few decades witness the burgeoning development of integrated circuit in terms of process technology scaling. Along with the tremendous benefits coming from the scaling, challenges are also presented in various stages. During the design time, the complexity of developing a circuit with millions to billions of smaller size transistors is extended after the variations are taken into account. The difficulty of analyzing these nondeterministic properties makes the allocation scheme of redundant resource hardly work in a cost-efficient way. Besides fabrication variations, analog circuits are suffered from severe performance degradations owing to their physical attributes which are vulnerable to aging effects. As such, the post-silicon calibration approach gains increasing attentions to compensate the performance mismatch. For the user-end applications, additional system failures result from the pirated and counterfeited devices provided by the untrusted semiconductor supply chain. Again analog circuits show their weakness to this threat due to the shortage of piracy avoidance techniques. In this dissertation, we propose three adaptive integrated circuit designs to overcome these challenges respectively. The first one investigates the variability-aware gate implementation with the consideration of the overhead control of adaptivity assignment. This design improves the variation resilience typically for digital circuits while optimizing the power consumption and timing yield. The second design is implemented as a self-validation system for the calibration of diverse analog circuits. The system is completely integrated on chip to enhance the convenience without external assistance. In the last design, a classic analog component is further studied to establish the configurable locking mechanism for analog circuits. The use of Satisfiability Modulo Theories addresses the difficulty of searching the unique unlocking pattern of non-Boolean variables