Enhanced electrodeposition for the filling of micro-vias

This thesis investigated the introduction of megasound (MS) (1MHz) acoustic technology as an enhanced agitation method of an electrolyte solution for the electrochemical deposition of copper (Cu), used in electroplating processes. The thesis, carried out at Merlin Circuit Technology Ltd, studied the possibility of improving processing capabilities for use in Printed Circuit Board (PCB) industrial manufacture. Prior laboratory experiments demonstrated increased metallisation of vertical interconnect access (via) features in a Printed Circuit Board (PCB), which, if applied within manufacturing, would enable increased connectivity throughout a PCB and result in cost savings. PCB manufacturing quality after MS-assisted Cu electroplating was assessed by measurements of the topography of the electrodeposits, using scanning electron microscopy and white-light interferometry. Cu plating rate changes were also measured on the surface of the PCB and inside the vias. After plating Cu with MS-assistance, the macro and microscale surface composition was demonstrated to alter due to the direct influence of the acoustic waves. Systematic characteristic of the surface was conducted by varying the settings of the acoustic transducer device as well as the process parameters including electrical current distribution, bath additive chemistry and solution temperature. MS processing was shown to produce unique Cu artefacts. Their deleterious formation was demonstrated to be influenced by acoustic standing waves and microbubble formations at the electrolyte solution/PCB interface. Causes of these artefacts, microfluidic streaming and cavitation, were also observed and controlled to reduce the creation of these artefacts. MS plating Cu down through-hole via (THV) and blind-via (BV) interconnects was shown to produce measureable benefits. These include, for THVs, a 700 % increase of Cu plating deposit thickness within a 175 μm diameter, depth-to-width aspect ratio (ar) of 5.7:1, compared with processing under no-agitation conditions. For BVs, a 60 % average increase in Cu deposition in 150 μm and 200 μm, ar 1:1, was demonstrated against plating under standard manufacturing conditions - bubble agitation and panel movement.Engineering and Physical Research Council (EPSRC) grant number EP/G037523/

Piin läpivientien luotettavuus ja elinikä termisessä rasituksessa

Through-silicon via (TSV) is one of the key technologies for three-dimensional (3D) integrated circuits (ICs). TSVs enable vertical electrical connections between components which greatly reduces interconnection lengths. Regardless of all the promise the technique has shown, there are still major obstacles surrounding reliability and the cost of fabrication of the TSV structure. The first part of the thesis is a literature survey that focuses on different failure mechanisms of TSVs. In addition, different fabrication and design choices of TSVs are presented with the focus being on their effect on reliability. The experimental part of the thesis presents reliability and lifetime assessment of tapered partially copper-filled blind TSVs under thermal cycling. The reliability test was carried out with nine samples. Six of them had 420 vias and three of them had 1400 vias in a daisy chain structure. Finite element method (FEM) was used to predict the critical failure locations of the TSV structure. Lifetime was predicted by Weibull analysis. The cross-sections of the test samples were prepared by molding, mechanical grinding and polishing and analyzed by scanning electron microscope (SEM). Electrical measurements showed almost constant resistance increase in the samples before failures were noticed. The first failed sample was noticed after 200 cycles and the last at 4000 cycles. Lifetime of TSVs under thermal cycling was proven to be acceptable with used failure criterion. According to Weibull analysis, about 10 % of the samples with 420 vias will break after 1000 cycles. Sample preparation for imaging was deemed sufficient although the grinding caused artifacts. The simulation results were compared with SEM micrographs. The images showed that the failures were located at the maximum stress areas, identified with FEM simulations, at the bottom of the via. From the SEM images, it was deduced that the defects initiated from the fabrication process and propagated due to maximum localized stress.Piin läpivienti -rakenteet ovat keskeisessä osassa kolmiulotteisten integroitujen piirien kehityksessä. Piin läpiviennit mahdollistavat komponenttien vertikaalin yhdistämisen toisiinsa, mikä lyhentää huomattavasti niiden välistä etäisyyttä. Kaikista hyvistä puolista huolimatta tekniikalla on vielä haasteita edessään. Niistä suurimmat liittyvät rakenteen luotettavuuteen ja valmistuskustannuksiin. Diplomityön kirjallisessa osuudessa keskitytään piin läpivientien erilaisiin vauriomekanismeihin. Sen lisäksi tutkitaan valmistus- ja suunnitteluratkaisujen vaikutusta läpivientien luotettavuuteen. Kokeellisen osan tarkoituksena on osittain kuparitäytettyjen kaventuvien piin läpivientien luotettavuuden ja eliniän määrittäminen termisessä syklaustestissä. Luotettavuustestaus suoritettiin yhdeksällä näytteellä, joista kuudessa oli 420 läpivientiä ja kolmessa 1400 läpivientiä ketjurakenteessa. Elementtimallintamisen avulla määritettiin kriittiset vauriokohdat läpivientirakenteessa ja elinikä määritettiin Weibull-analyysillä. Näytteiden poikkileikkauksien valmistamiseen käytettiin muovaamista, mekaanista hiomista ja kiillotusta ja analysointi suoritettiin pyyhkäisyelektronimikroskoopilla. Näytteiden resistanssi nousi tasaisesti ennen rikkoutumisten havaitsemista. Ensimmäinen rikkoutuminen huomattiin 200 syklin jälkeen ja viimeinen 4000 syklin kohdalla. Näytteiden luotettavuus osoittautui hyväksi käytetyillä kriteereillä. Weibull-analyysin mukaan 10 % 420 läpiviennin näytteistä rikkoutuu 1000 syklin jälkeen. Karkea arvio voidaan tehdä, että satunnainen läpivienti rikkoutuu 0,024 % todennäköisyydellä 1000 syklin jälkeen. Pyyhkäisyelektronimikroskoopin kuvien perusteella havaittiin, että näytteet rikkoutuivat maksimaalisen rasituksen alueella läpivientien alaosassa. Kuvien perusteella päädyttiin johtopäätökseen, että näytteiden rikkoutumisen aiheuttivat virheet, jotka ovat peräisin valmistusprosessista ja jotka etenivät rakenteessa termisen rasituksen vaikutuksesta

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications

Novel fine pitch interconnection methods using metallised polymer spheres

There is an ongoing demand for electronics devices with more functionality while reducing size and cost, for example smart phones and tablet personal computers. This requirement has led to significantly higher integrated circuit input/output densities and therefore the need for off-chip interconnection pitch reduction. Flip-chip processes utilising anisotropic conductive adhesives anisotropic conductive films (ACAs/ACFs) have been successfully applied in liquid crystal display (LCD) interconnection for more than two decades. However the conflict between the need for a high particle density, to ensure sufficient the conductivity, without increasing the probability of short circuits has remained an issue since the initial utilization of ACAs/ACFs for interconnection. But this issue has become even more severe with the challenge of ultra-fine pitch interconnection. This thesis advances a potential solution to this challenge where the conductive particles typically used in ACAs are selectively deposited onto the connections ensuring conductivity without bridging. The research presented in this thesis work has been undertaken to advance the fundamental understanding of the mechanical characteristics of micro-sized metal coated polymer particles (MCPs) and their application in fine or ultra-fine pitch interconnections. This included use of a new technique based on an in-situ nanomechanical system within SEM which was utilised to study MCP fracture and failure when undergoing deformation. Different loading conditions were applied to both uncoated polymer particles and MCPs, and the in-situ system enables their observation throughout compression. The results showed that both the polymer particles and MCP display viscoelastic characteristics with clear strain-rate hardening behaviour, and that the rate of compression therefore influences the initiation of cracks and their propagation direction. Selective particle deposition using electrophoretic deposition (EPD) and magnetic deposition (MD) of Ni/Au-MCPs have been evaluated and a fine or ultra-fine pitch deposition has been demonstrated, followed by a subsequent assembly process. The MCPs were successfully positively charged using metal cations and this charging mechanism was analysed. A new theory has been proposed to explain the assembly mechanism of EPD of Ni/Au coated particles using this metal cation based charging method. The magnetic deposition experiments showed that sufficient magnetostatic interaction force between the magnetized particles and pads enables a highly selective dense deposition of particles. Successful bonding to form conductive interconnections with pre-deposited particles have been demonstrated using a thermocompression flip-chip bonder, which illustrates the applicable capability of EPD of MCPs for fine or ultra-fine pitch interconnection

Kupari-tina mikroliitosten karakterisointimenetelmät

The microelectronics industry constantly aspires to shrink the device features. At the package level, this implies a decrease in the interconnect size leading to small volume interconnections that are commonly called micro-connects. Smaller material volumes may give rise to new reliability challenges, such as open circuits, due to Kirkendall voiding. The root cause(s) for Kirkendall voiding is not yet clear and the methods for characterization are still varied. This thesis reviews techniques to characterize the microstructure and impurities in Cu-Sn micro-connects. The evaluated techniques are Auger Electron Spectroscopy (AES), Electron Energy Loss Spectroscopy (EELS), Energy-Dispersive X-Ray Spectroscopy (EDX), X-Ray Spectroscopy (XPS), Secondary Ion Mass Spectrometry (SIMS), Rutherford Backscattering Spectrometry (RBS), Elastic Recoil Detection Analysis (EELS), Transmission Electron Microscopy (TEM), Focused Ion Beam (FIB), and Scanning Acoustic Microscopy (SAM). From the reviewed techniques, EDX, FIB, SAM, and TEM are used in the experimental section. For the first time, impurities are measured directly inside Kirkendall voids. It was discovered that the Kirkendall voids in annealed Cu-Sn samples contained a significant amount of chlorine and oxygen. The ASTM grain size counting method was applied to FIB-polished samples. It was observed that the grain size did not increase by annealing at 150 ◦C. Furthermore, for the first time, GHz-SAM was used to characterize Kirkendall voids. The technique is promising but it is still affected by the low lateral resolution.Mikroelektroniikkateollisuus pyrkii jatkuvasti pienentämään laitekokoa. Paketointitasolla tämä tarkoittaa sitä, että sirujen välisten liitosten kokoluokka on siirtymässä kohti mikroliitoksia, jotka saattavat aiheuttaa uusia luotettavuusongelmia. Kirkendall-aukot ovat yksi syy kyseisiin luotettavuusongelmiin ja aukkojen alkuperä on vielä tuntematon. Sen lisäksi, mikroliitosten ja Kirkendall aukkojen karakterisointiin käytetään toisistaan poikkeavia menetelmiä eikä sopivista metodeista ole vielä yhteisymmärrystä. Tämä diplomityö tarkastelee kupari-tina mikroliitoksien mikrorakenteen ja epäpuhtauksien analysointiin käytettyjä menetelmiä. Tarkasteltavat menetelmät ovat Auger elektronispektroskopia (AES), epäelastinen elektronisironta (EELS), energiadispersiivinen röntgenspektroskopia (EDX), röntgenfotoelektronispektroskopia (XPS), sekundääri ionimassaspektroskopia (SIMS), Rutherford-takaisinsirontaspektroskopia (RBS), rekyylispektrometria (ERDA), läpäisyelektronimikroskopia (TEM), keskitetty ionisuihku (FIB) ja akustinen mikroskopia (SAM). Esitellyistä menetelmistä kokeellisessa osiossa käytettiin EDX:ää, FIB:ä, SAM:a ja (S)TEM:ä. Tässä diplomityössä on mitattu ensimmäistä kertaa epäpuhtauksia Kirkendall-aukkojen sisältä. Mittauksista saatiin selville, että hehkutettujen kupari-tina -näytteiden Kirkendall-aukot sisälsivät huomattavan määrän happea ja klooria. Raekokoa tarkasteltiin kiillottamalla näytteet FIB:llä ja soveltamalla ASTM:n raekoko -standardia. Työssä huomattiin, että raekoko ei kasvanut, jos näytteitä hehkutettiin 150 ◦C lämpötilassa. Tämä on myös ensimmäinen kerta, kun GHzSAM:a on käytetty Kirkendall-aukkojen tutkimiseen. Tulokset olivat lupaavia, mutta menetelmän alhainen sivuttaissuuntainen resoluutio on vielä rajoittava tekijä

Characterization of Nanomaterials: Selected Papers from 6th Dresden Nanoanalysis Symposiumc

This Special Issue “Characterization of Nanomaterials” collects nine selected papers presented at the 6th Dresden Nanoanalysis Symposium, held at Fraunhofer Institute for Ceramic Technologies and Systems in Dresden, Germany, on 31 August 2018. Following the specific motto of this annual symposium “Materials challenges—Micro- and nanoscale characterization”, it covered various topics of nanoscale materials characterization along the whole value and innovation chain, from fundamental research up to industrial applications. The scope of this Special Issue is to provide an overview of the current status, recent developments and research activities in the field of nanoscale materials characterization, with a particular emphasis on future scenarios. Primarily, analytical techniques for the characterization of thin films and nanostructures are discussed, including modeling and simulation. We anticipate that this Special Issue will be accessible to a wide audience, as it explores not only methodical aspects of nanoscale materials characterization, but also materials synthesis, fabrication of devices and applications

Advanced Back-End Processing Techniques For Infrared Focal Plane Arrays

With the continued scaling of infrared focal plane array (FPA) pixel pitch down to the diffraction limit, current backend processing techniques are becoming less viable. For one class of detectors, FPAs are formed when pixels of a detector array are electrically connected to analogous elements on a separate readout integrated circuit (ROIC) chip with malleable In bumps. Currently, these In bumps are formed by a standard thick photoresist liftoff process. Maintaining high connectivity with this process becomes difficult or impossible as pitch is reduced because of liftoff failure due to the increased aspect ratio required of bumps. Another class of infrared FPAs epoxies the detector array to the ROIC. A via is etched through the detector material of each pixel down to ROIC contact pads. Interconnects are currently formed by evaporating metal into the via, linking the detector array to the ROIC. As pixel pitch is reduced, obtaining proper interconnect becomes increasingly difficult due to the line of sight requirement of evaporation. In this work, two novel techniques to realize reduced pitch interconnects were developed and demonstrated that do not have the limitations of current techniques. For In-based FPAs, a template transfer process was developed that does not require a thick liftoff process. In this technique, In bumps are formed by electroplating on a separate, patterned template wafer and then transferred to the detector array or ROIC using a flip-chip bonder. A low-friction, amorphous fluoropolymer was used to shape the bumps and encourage transfer from the template wafer. A proof of principle for this process was obtained, demonstrating the transfer of 5.5 micron thick, 10 micron pitch In bumps to a mechanical ROIC. For the via-based FPAs, interconnection was achieved by electrochemical deposition of Ni films. Both electroplated and electroless Ni processes were developed for this purpose. After confirming the compatibility of these processes with detector and ROIC materials, Ni was plated into the vias of active HgCdTe photodetectors. This resulted in diffusion limited I-V characteristics that were stable through thermal cycling. Electroless Ni via contacts formed on an active 5 micron pitch FPA resulted in 99.94% connectivity

Electroless metallisation of glass for electrical interconnect applications

The microelectronics industry requires continuous advances due to ever-evolving technology and the corresponding need for higher density substrates with smaller features. Specifically, new dielectric materials with enhanced electrical properties are needed. At the same time, adhesion must be maintained in order to preserve package reliability and mechanical performance. As a result, this research investigates the use of thin glass sheets as an alternative substrate material as it offers a number of advantages including coefficient of thermal expansion similar to silicon, good dielectric properties and optical transparency to assist in the alignment of buried features. As part of this project it was necessary to deposit metallic coatings onto the glass sheets to create electrical tracks, pads and microvias. In order to meet these requirements, the metallisation of both smooth as received glass surfaces and surfaces roughened by laser machining using electroless copper and nickel deposition were investigated. This study resulted in a number of important conclusions about the roles of chemical bonding and mechanical anchoring in both the adhesion and catalyst adsorption, that are key factors in the electroless metallisation process.....EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Nanostructured porous materials form Micro- and nano-electronics applications

This thesis work presents new research on porous silicon technologies for the heterogeneous integration on silicon platforms, as a key enabling technology for future 3D integrated systems. Porous silicon can be obtained with CMOS compatible processes on localized area on silicon wafer and, due to its tunable electrical, mechanical and thermal characteristics is an effective buffer material. Moreover, macroporous morphologies of porous silicon can can be exploited for the realization of “bed-of-nails” type through wafer interconnects, paving the way to high density, low-cost, through silicon vias. This work is divided in three parts: the first part introduces porous silicon, summarizes the available literature and presents process characterization for the porous layers obtained in this work and their properties; the second part describes the layer transfer technology and the buried cavities technologies developed in this work using the porous layers presented in the previous part; the last part introduces two applications of the layer transfer technology: compliant contacts and integrated physically small antennas

X-ray diffraction techniques for future advanced CMOS metrology challenges

Traditional Si CMOS scaling following Moore’s Law is becoming increasingly difficult as physical limits are approached at sub-20 nm nodes and beyond. A significant issue is the limited charge carrier mobility in Si, and so new channel materials that carry relatively higher mobility carriers have been used, such as strained Si. Other materials such as III-V and germanium (Ge) are currently under consideration for replacing the conventional Si channel for future generations of low power and high speed electronics. However, challenges still remain with the realisation of high quality III-V material on Si for CMOS devices fabrication because the tolerance to dislocations is very low (<105 cm-2). In order to overcome this problem, a non-destructive X-ray characterisation routine which can be used to effectively help III-V growers identify various issues associated with heteroepitaxial growth of III-V materials and which delivers useful experimental feedback to growers for material quality optimisation has been designed. The feasibility of this routine has been demonstrated through the characterisation of a series of deliberately fabricated “problematic” heteroepitaxial GaAs materials. According to industry experts, the future of modern nanoelectronics may well also depend on a second trend, which is the implementation of diverse functionality within modern ICs. This “More than Moore” (MtM) approach will be realised through the manufacture of complex Systems on Chip (SoC) and Systems in Package (SiP), evolving towards fully three-dimensional ICs (3-D ICs). However, progress in this direction is hampered by the lack of a compelling metrology in order to measure non-destructively and in situ the process induced warpage, strain and other defects inside silicon die, a problem which has been highlighted by the International Technology Roadmap for Semiconductors (ITRS). Therefore, the second aim of this thesis has been the development of a novel laboratory-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) in order to address this major stumbling block in the development of MtM integrated circuit technology