Variability-Aware Design of Subthreshold Devices

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device

Impact of self-heating on the statistical variability in bulk and SOI FinFETs

In this paper for the first time we study the impact of self-heating on the statistical variability of bulk and SOI FinFETs designed to meet the requirements of the 14/16nm technology node. The simulations are performed using the GSS ‘atomistic’ simulator GARAND using an enhanced electro-thermal model that takes into account the impact of the fin geometry on the thermal conductivity. In the simulations we have compared the statistical variability obtained from full-scale electro-thermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electro-thermal simulations. The combined effects of line edge roughness and metal gate granularity are taken into account. The distributions and the correlations between key figures of merit including the threshold voltage, on-current, subthreshold slope and leakage current are presented and analysed

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology

A simple device-level characterization approach to quantitatively evaluate the impacts of different random variation sources in FinFETs is proposed. The impacts of random dopant fluctuation are negligible for FinFETs with lightly doped channel, leaving metal gate granularity and line-edge roughness as the two major random variation sources. The variations of Vth induced by these two major categories are theoretically decomposed based on the distinction in physical mechanisms and their influences on different electrical characteristics. The effectiveness of the proposed method is confirmed through both TCAD simulations and experimental results. This letter can provide helpful guidelines for variation-aware technology development

Analysis and comprehensive analytical modeling of statistical variations in subthreshold MOSFET's high frequency characteristics

In this research, the analysis of statistical variations in subthreshold MOSFET's high frequency characteristics defined in terms of gate capacitance and transition frequency, have been shown and the resulting comprehensive analytical models of such variations in terms of their variances have been proposed. Major imperfection in the physical level properties including random dopant fluctuation and effects of variations in MOSFET's manufacturing process, have been taken into account in the proposed analysis and modeling. The up to dated comprehensive analytical model of statistical variation in MOSFET's parameter has been used as the basis of analysis and modeling. The resulting models have been found to be both analytic and comprehensive as they are the precise mathematical expressions in terms of physical level variables of MOSFET. Furthermore, they have been verified at the nanometer level by using 65~nm level BSIM4 based benchmarks and have been found to be very accurate with smaller than 5 % average percentages of errors. Hence, the performed analysis gives the resulting models which have been found to be the potential mathematical tool for the statistical and variability aware analysis and design of subthreshold MOSFET based VHF circuits, systems and applications

Comprehensive Analytical Models of Random Variations in Subthreshold MOSFET’s High-Frequency Performances

Subthreshold MOSFET has been adopted in many low power VHF circuits/systems in which their performances are mainly determined by three major high-frequency characteristics of intrinsic subthreshold MOSFET, i.e., gate capacitance, transition frequency, and maximum frequency of oscillation. Unfortunately, the physical level imperfections and variations in manufacturing process of MOSFET cause random variations in MOSFET’s electrical characteristics including the aforesaid high-frequency ones which in turn cause the undesired variations in those subthreshold MOSFET-based VHF circuits/systems. As a result, the statistical/variability aware analysis and designing strategies must be adopted for handling these variations where the comprehensive analytical models of variations in those major high-frequency characteristics of subthreshold MOSFET have been found to be beneficial. Therefore, these comprehensive analytical models have been reviewed in this chapter where interesting related issues have also been discussed. Moreover, an improved model of variation in maximum frequency of oscillation has also been proposed

2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application

Traditional memory devices are facing more challenges due to continuous down-scaling. 6T-SRAM suffers from variability [1-2] and reliability [3-4] issues, which introduce cell stability problems. DRAM cells with one transistor, one capacitor (1T1C) struggle to maintain refresh time [5-6]. Efforts have been made to find new memory solutions, such as one transistor (1T) solutions [7-9]. Floating body based memory structures are among the potential candidates, but impact ionization or band-to-band tunnelling (B2BT) limits their refresh time [10]. A recently proposed zero impact ionization and zero subthreshold swing device named Z2FET [9, 11-12] has been demonstrated and is a promising candidate for 1T DRAM memory cell due to technology advantages such as CMOS technology compatibility, novel capacitor-less structure and sharp switching characteristics. In the Z2FET memory operation, refresh frequency is determined by data retention time. Previous research [11-12] is lacking systematic simulation analysis and understanding on the underlying mechanisms. In this paper, we propose a new simulation methodology to accurately extract retention time in Z2FET devices and understand its dependency on applied biases, temperatures and relevant physical mechanisms. Since the stored ‘1’ state in Z2FET is an equilibrium state [9, 11-12] and there is no need to refresh, we will concentrate on state ‘0’ retention. Two types of ‘0’ retention time: HOLD ‘0’ and READ ‘0’ retention time will be discussed separately

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits