Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1669

Terabit Burst Switching Final Report

This is the final report For Washington University\u27s Terabit Burst Switching Project, supported by DARPA and Rome Air Force Laboratory. The primary objective of the project has been to demonstrate the feasibility of Burst Switching, a new data communication service, which seeks to more effectively exploit the large bandwidths becoming available in WDM transmission systems. Burst switching systems dynamically assign data bursts to channels in optical datalinks, using routing information carried in parallel control channels

General Mutual Exclusion Primitive

Computer Scienc

Advanced microstructured platforms for neuroscience: from lab-on-chips for circadian clock studies to next generation bionic 3D brain tissue models

In mammals, the suprachiasmatic nucleus (SCN) of the hypothalamus is considered the master circadian pacemaker which coordinates circadian rhythms in the central nervous system (CNS) and across the entire body. The SCN receives light input from the eyes through the retinohypothalamic tract and then it synchronizes other clocks in the CNS and periphery, thus orchestrating rhythms throughout the body. However, little is known about how so many cellular clocks within and across brain circuits can be effectively synchronized to entrain the coordinated expression of clock genes in cells distributed all over the brain. In this work I investigated the possible implication of two possible pathways: i) paracrine factors-mediated synchronization and ii) astrocytes-mediated synchronization. To study these pathways, I adopted an in vitro research model that I developed based on a lab-on-a-chip microfluidic device designed and realized in our laboratory. This device allows growing and compartmentalizing distinct neural populations connected through a network of astrocytes or through a cell-free channel in which the diffusion of paracrine factors is allowed. By taking advantage of this device, upon its validation, I synchronized neural clocks in one compartment and analyzed, in different experimental conditions, the induced expression of clock genes in a distant neural network grown in the second compartment. Results show that both pathways can be involved, but might have different roles. Neurons release factors that can diffuse to synchronize a neuronal population. The same factors can also synchronize astrocytes that, in turn, can transmit astrocyte-mediated molecular clocks to more distant neuronal populations. This is supported by experimental data obtained using microfluidic devices featuring different channel lengths. I found that paracrine factors-mediated synchronization occurs only in the case of a short distance between neuronal populations. On the contrary, interconnecting astrocytes define an active channel that can transfer molecular clocks to neural populations also at long distances. The study of possibly involved signaling factors indicate that paracrine factors-mediated synchronization occurs through GABA signaling, while astrocytes-mediated synchronization involves both GABA and glutamate. These findings strength the importance of the synergic regulation of clock genes among neurons and astrocytes, and identify a previously unknown role of astrocytes as active cells in distributing signals to regulate the expression of clock genes in the brain. Preliminary results also show a correlation between astrocyte reactivity and local alterations in neuronal synchronization, thus opening a new scenario for future studies in which disease-induced astrocyte reactivity might be linked to alterations in clock gene expression.Three-dimensional (3D) brain models hold great potential for the generation of functional in vitro models to advance studies on human brain development, diseases and possible therapies. The routine exploitation of such models, however, is hindered by the lack of technologies to chronically monitor the activity of neural aggregates in three dimensions. A promising new approach consists in growing bio-artificial 3D brain model systems with seamless tissue-integrated biosensing artificial microdevices. Such devices could provide a platform for in-tissue sensing of diverse biologically relevant parameters. To date there is very little information on how to control the extracellular integration of such microscale devices into neuronal 3D cell aggregates. In this direction, in the present work I contributed to investigated the growth of hybrid neurospheroids obtained by the aggregation of silicon sham microchips (100x100x50\u3bcm3) with primary cortical cells. Interestingly, by coating microchips with different adhesion-promoting molecules, we reveal that surface functionalization can tune the integration and final 3D location of self-standing microdevices into neurospheroids. Morphological and functional characterization suggests that the presence of an integrated microdevice does not alter spheroid growth, cellular composition, nor network activity and maturation. Finally, we also demonstrate the feasibility of separating cells and microchips from formed hybrid neurospheroids for further single-cell analysis, and quantifications confirm an unaltered ratio of neurons and glia. These results uncover the potential of surface-engineered self-standing microdevices to grow untethered three-dimensional brain-tissue models with inbuilt bioelectronic sensors at predefined sites

NASA Thesaurus. Volume 1: Hierarchical listing

There are 16,713 postable terms and 3,716 nonpostable terms approved for use in the NASA scientific and technical information system in the Hierarchical Listing of the NASA Thesaurus. The generic structure is presented for many terms. The broader term and narrower term relationships are shown in an indented fashion that illustrates the generic structure better than the more widely used BT and NT listings. Related terms are generously applied, thus enhancing the usefulness of the Hierarchical Listing. Greater access to the Hierarchical Listing may be achieved with the collateral use of Volume 2 - Access Vocabulary

NASA thesaurus. Volume 1: Hierarchical Listing

There are over 17,000 postable terms and nearly 4,000 nonpostable terms approved for use in the NASA scientific and technical information system in the Hierarchical Listing of the NASA Thesaurus. The generic structure is presented for many terms. The broader term and narrower term relationships are shown in an indented fashion that illustrates the generic structure better than the more widely used BT and NT listings. Related terms are generously applied, thus enhancing the usefulness of the Hierarchical Listing. Greater access to the Hierarchical Listing may be achieved with the collateral use of Volume 2 - Access Vocabulary and Volume 3 - Definitions

Advanced Coding And Modulation For Ultra-wideband And Impulsive Noises

The ever-growing demand for higher quality and faster multimedia content delivery over short distances in home environments drives the quest for higher data rates in wireless personal area networks (WPANs). One of the candidate IEEE 802.15.3a WPAN proposals support data rates up to 480 Mbps by using punctured convolutional codes with quadrature phase shift keying (QPSK) modulation for a multi-band orthogonal frequency-division multiplexing (MB-OFDM) system over ultra wideband (UWB) channels. In the first part of this dissertation, we combine more powerful near-Shannon-limit turbo codes with bandwidth efficient trellis coded modulation, i.e., turbo trellis coded modulation (TTCM), to further improve the data rates up to 1.2 Gbps. A modified iterative decoder for this TTCM coded MB-OFDM system is proposed and its bit error rate performance under various impulsive noises over both Gaussian and UWB channel is extensively investigated, especially in mismatched scenarios. A robust decoder which is immune to noise mismatch is provided based on comparison of impulsive noises in time domain and frequency domain. The accurate estimation of the dynamic noise model could be very difficult or impossible at the receiver, thus a significant performance degradation may occur due to noise mismatch. In the second part of this dissertation, we prove that the minimax decoder in \cite, which instead of minimizing the average bit error probability aims at minimizing the worst bit error probability, is optimal and robust to certain noise model with unknown prior probabilities in two and higher dimensions. Besides turbo codes, another kind of error correcting codes which approach the Shannon capacity is low-density parity-check (LDPC) codes. In the last part of this dissertation, we extend the density evolution method for sum-product decoding using mismatched noises. We will prove that as long as the true noise type and the estimated noise type used in the decoder are both binary-input memoryless output symmetric channels, the output from mismatched log-likelihood ratio (LLR) computation is also symmetric. We will show the Shannon capacity can be evaluated for mismatched LLR computation and it can be reduced if the mismatched LLR computation is not an one-to-one mapping function. We will derive the Shannon capacity, threshold and stable condition of LDPC codes for mismatched BIAWGN and BIL noise types. The results show that the noise variance estimation errors will not affect the Shannon capacity and stable condition, but the errors do reduce the threshold. The mismatch in noise type will only reduce Shannon capacity when LLR computation is based on BIL

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout