22 research outputs found

    Development of tools for the simulation of nanometric transistors using advanced computational architectures

    Get PDF
    The aim of this thesis project is the study of nanoscale semiconductor devices, including new options based on new architectures and designs, for which multidimensional simulation tool based on Monte-Carlo models are going to be developed, including quantum corrections by solving the Schrödinger equation in the transverse direction to the propagation of carriers within the device. So far, our research group has developed several simulators semiconductor devices using various simulation techniques. This work is developed in collaboration with several national and international groups. It should primarily highlight the group maintains collaborations with the universities of Glasgow, Swansea and Granada and gives rise to this thesis project.The ultimate goal is to use the simulator to study various optimized, especially classical electronic devices, SOI-based and multigate, with silicon devices for sizes of under 10 nm

    Electrical Characterisation of III-V Nanowire MOSFETs

    Get PDF
    The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

    Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions

    Get PDF

    Electrical and temperature characterisation of silicon and germanium nanowire transistors based on channel dimensions

    Get PDF
    Amongst various sensing and monitoring technologies, sensors based on field effect transistors (FETs) have attracted considerable attention from both the industry and academia. Owing to their unique characteristics such as their small size, lightweight, low cost, flexibility, fast response, stability and ability for further downscaling, nanowire transistors (NWTs) can serve as ideal nanosensors and successors to FET-based nanoscale devices. However, as the dimensions (length, diameter and oxide thickness) of NWT channels are shrinking down, the electrical and temperature characteristics of NWTs are affected, thereby degrading the transistor performance. Although the applications of NWTs as biological and/or chemical sensors have been extensively explored in the literature, the use of these transistors as temperature sensors has been largely ignored. Consequently, this research investigates the impact of the cross-sectional dimensions of silicon nanowire transistors (SiNWTs) and germanium nanowire transistors (GeNWTs) on their electrical and temperature characteristics. Accordingly, evaluate and compare the performance of the considered nanowires and their potential applicability as temperature nanosensors for continuous temperature monitoring with good detection capability, high flexibility and low cost. A comprehensive simulation-based comparative study is performed by using six variable parameters, namely, gate length (Lg), channel diameter (Dch), oxide thickness (Tox), ambient temperature (T), gate bias voltage (Vg) and drain bias voltage (VDD). The impact of changes in these parameters on the electrical and temperature characteristics of SiNWTs and GeNWTs is then evaluated. The well-known MuGFET simulation tool for nanoscale multi-gate FET structure is used for the experimental simulations. A wide range of variable parameters are simulated in three simulation-based case studies, which cover 21 operating voltages and an ambient temperature increasing from 225 K to 450 K by a step of 25 K. The first case study considers the variation in gate length (Lg = 25, 45, 65, 85 and 105 nm), the second focuses on the variation in channel diameter (Dch = 10, 20, 40 and 80 nm) and the third focuses on the variation in channel oxide thickness (Tox = 1, 2, 3, 4 and 5 nm). Four performance evaluation metrics are considered, namely, subthreshold swing (SS), threshold voltage (Vth), drain-induced barrier lowering (DIBL) and drain current variation rate, ∆Id, which serves as an indicator of temperature sensitivity. The optimal stability- and sensitivity-based performance of NWTs can be achieved at certain optimal operating voltages with the SS values closer to the ideal state, a lower DIBL level and higher voltage threshold values. The simulation results for SiNWTs and GeNWTs highlight the effects of varying the channel dimensions (Lg, Dch, and Tox) on their temperature and electrical characteristics. Specifically, the temperature sensitivity (∆Id) of SiNWTs and GeNWTs significantly increased along with various channel dimensions and operating temperatures, and the optimal operating voltages are identified for each NWT. According to their temperature characteristics, SiNWTs show higher stability to ambient temperature variations compared with GeNWTs, which in turn demonstrate a higher sensitivity in all cases compared with SiNWT. In addition, SiNWTs outperform GeNWTs in terms of SS and Vth and demonstrate a faster switching speed and lower leakage current given that the values of SS are very close to the ideal state and high threshold voltages. SiNWTs also achieve a high DIBL level in certain cases, which is considered acceptable for most channel dimensions. The impact of changing the gate length on the behaviour of NWTs is very obvious, and varying the oxide thickness demonstrates the lowest impact. SiNWTs have high potential to be applied as temperature nanosensors due to their electrical and temperature stability

    Miniaturized Transistors, Volume II

    Get PDF
    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

    Get PDF
    Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of Inx≥0.53Ga1-xAs/In0.52Al0.48As and Inx≥0.1Ga1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm2/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In0.85Ga0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (Lside) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH4)2S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al2O3/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×1012cm-2eV-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (Id,sat=1.14mA/mm), double peaked transconductance (gm=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (Ron=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of Id,sat (11×), gm (5.5×) and Ron (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (Lside) from 1μm down to 70nm improved Id,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In0.3Ga0.7Sb-channel (Id,sat=49.4mA/mm, gm=12.3mS/mm, Ron=31.7kΩ.μm) and In0.4Ga0.6Sb-channel (Id,sat=38mA/mm, gm=11.9mS/mm, Ron=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS

    Study of High-k Dielectrics and their Interfaces on Semiconductors for Device Applications

    Get PDF
    This thesis has focused on two emerging applications of high-k dielectrics in Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and in Metal-InsulatorSemiconductor High Electron Mobility Transistors (MIS-HEMTs). The key aim has been to propose the best routes for passivation of semiconductor/high-k oxide interfaces by investigating the band alignments and interface properties of several oxides, such as Tm2O3, Ta2O5, ZrO2, Al2O3 and MgO, deposited on different semiconductors: Si, Ge, GaN, InGaAs and InGaSb. The electrical characterisation of fabricated MIS capacitor and (MIS)-HEMT devices have also been performed. Thulium silicate (TmSiO) has been identified as a promising candidate for integration as interfacial layer (IL) in HfO2/TiN MOSFETs. The physical properties of Tm2O3/IL/Si interface have been elucidated, where IL (TmSiO) has been formed using different post-deposition annealing (PDA) temperatures, from 550 to 750 °C. It has been found that the best-scaled stack (sub-nm IL) is formed at 550 °C PDA with a graded interface layer and a strong SiOx (Si 3+) component. A large valence band offset (VBO) of 2.8 eV and a large conduction band offset (CBO) of 1.9 eV have been derived for Tm2O3/Si by X-ray photoelectron spectroscopy (XPS) and variable angle spectroscopic ellipsometry. Further increase of device performance can be achieved by replacing Si with GaN for high frequency, high power and high-temperature operation. In this thesis, several GaN cleaning procedures have been considered: 30% NH4OH, 20% (NH4)2S, and 37% HCl. It has been found that the HCl treatment shows the lowest oxygen contamination and Garich surface, and hence has been used prior sputtering of Ta2O5, Al2O3, ZrO2 and MgO on GaN. The large VBOs of 1.1 eV and 1.2 eV have been derived for Al2O3 and MgO on GaN respectively, using XPS and Kraut’s method; the corresponding CBOs are 2.0 eV and 2.8 eV respectively, taking into account the band gaps of Al2O3 (6.5 eV) and MgO (7.4 eV) determined from XPS O 1s electron energy spectra. The lowest leakage currents were obtained for devices with Al2O3 and MgO, i.e. 5.3 ×10-6 A/cm2 and 3.2 ×10-6 A/cm2 at 1 V, respectively in agreement with high band offsets (> 1 eV). Furthermore, the effect of different surface treatments (HCl, O2 plasma and 1-Octadecanethiol (ODT)) prior to atomic layer deposition of Al2O3 on the GaN/AlGaN/GaN heterostructure has been investigated. The MIS-HEMTs fabricated using the low-cost ODT GaN surface treatment have been found to exhibit superior performance for power switching applications such as a low threshold voltage, VT of -12.3 V, hysteresis of 0.12 V, a small subthreshold voltage slope (SS) of 73 mV/dec, and a low density of interface states, Dit of 3.0 x10^12 cm-2eV-1. A comprehensive novel study of HfO2/InGaAs and Al2O3/InGaSb interfaces have also been conducted for use in III-V based MOSFETs. The addition of the plasma H2/TMA/H2 pre-cleaning has been found to be very effective in recovering etch damage on InGaAs, especially for (110) orientation, and led to the improvement of electrical characteristics. Furthermore, the combination of H2 plasma exposure and forming gas anneal yielded significantly improved metrics for Al2O3/InGaSb over the control HCltreated sample, with the 150 W plasma treatment giving both the highest capacitance and the lowest stretch out

    Novel III-V compound semiconductor technologies for low power digital logic applications

    Get PDF
    As silicon (Si) complementary metal oxide semiconductor (CMOS) technology continues to scale into the 10 nm node, chip power consumption is approaching 200 W/cm2 and any further increase is unsustainable. Incorporating III-V compound semiconductor n-type devices into future CMOS generations could allow for the the reduction in supply voltage, and therefore, power consumption, while simultaneously improving on-state performance. The advanced state of Si CMOS places stringent demands on III-V devices, however: the current 14 nm Si tri-gate devices employ high aspect ratio, densely spaced fins which serve to significantly increase current per chip surface area. III-V devices need to significantly out perform state of the art Si devices in order to merit their disruptive incorporation into the well established CMOS process. This necessitates that they too exploit the vertical dimension. To this end, this thesis reports on the fabrication, measurement and analysis of high aspect ratio junctionless InGaAs FinFETs. The junctionless architecture was first demonstrated in 2010 and was shown to circumvent pro- hibitive fabrication challenges for devices with ultra short gate lengths. This work investigated the impact of fin width on both the on and off-state performance of 200 nm gate length devices, with nominal fin widths of 10, 15 and 20 nm. Excellent subthreshold performance was demonstrated, with the narrowest fin width exhibiting a minimum subthreshold swing (SS) of 73 mV/Dec., and an average SS of 80 mV/Dec. over two decades of current. A maximum on-current, Ion, of 80.51 μA/cm2 was measured at a gate overdrive of 0.5 V from an off-state current, Ioff, of 100 nA/cm2 and a drain voltage, Vd, of 0.5 V, with current normalised by gated perimeter. This is competitive with other III-V junctionless devices at similar gate lengths. With current normalised to base fin width, however, Ion increases to 371.8 μA/cm2, which is a record value among equivalently normalised non-planar III-V junctionless devices at any gate length. This technology, therefore, clearly demonstrates the feasibility of incorporating scaled, etched InGaAs fins into future logic generations. Perhaps the greatest bottleneck to the incorporation of III-V compounds into future CMOS technology nodes, however, is the lack of a suitable III-V PMOS candidate: co-integrating different material systems onto a common substate incurs great fabrication complexity, and therefore, cost. III-V antimonides, however, have recently emerged as promising candidates for III-V PMOS and exhibit the highest bulk electron mobility of all III-Vs in addition to a hole mobility second only to germanium. InGaSb ternary compounds have been shown to offer the best combined performance for electrons and holes in the same material, and as such, have the potential to the enable the most simplistic incarnation of III-V CMOS; provided, of course, that is possible to form a gate stack to both device polarities with sufficient electrical properties. To date, however, there has been no investigation into the high-k dielectric interface to InGaSb. To this end, this thesis presents results of the first investigation into the impact of in-situ H2 plasma exposure on the electrical properties of the p/n-In0.3Ga0.7Sb-Al2O3 interface. The parameter space was explored systematically in terms of H2 plasma power and exposure time, and further, the impact of impact of in-situ trimethylaluminium (TMA) pre-cleaning and annealing in forming gas was assessed. Metal oxide semiconductor capacitors (MOSCAPs) were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the correspond- ing capacitance-voltage and conductance-voltage measurements were analysed both qualita- tively and quantitatively via the simulation of an equivalent circuit model. X-Ray photoelectron spectroscopy (XPS) analysis of samples processed as part of the plasma power series revealed a combination of ex-situ HCl cleaning and in-situ H2 plasma exposure to completely remove In and Sb sub oxides, with the Ga-O content reduced to Ga-O:InGaSb <0.1. The optimal process, which included ex-situ HCl surface cleaning, in-situ H2 plasma and TMA pre-cleaning, and a post gate metal forming gas anneal, was unequivocally demonstrated to yield a fully unpinnned MOS interface with both n and p-type MOSCAPs explicitly demonstrating a genuine minority carrier response. Interface state and border trap densities were extracted, with a minimum Dit of 1.73x1012 cm-2 eV-1 located at ~110 meV below the conduction band edge and peak border trap densities approximately aligned with the valence and conduction band edges of 3x1019 cm-3 eV-1 and 6.5x1019 cm-3 eV-1 respectively. These results indicate that the optimal gate stack process is indeed applicable to both p and n- type InGaSb MOSFETs, and therefore, represent a critical advancement towards achieving high performance III-V CMOS

    Gold free ohmic contacts for III-V MOSFET devices

    Get PDF
    Over the past forty years the development of CMOS has been able to follow Moore’s law using planar silicon technology. However, this technology is reaching its limits as the density of transistors has a significant impact on the power dissipation in an integrated circuit. Alternative channel materials and device architectures will then be required in the future to reduce the power consumption of transistors. The development of CMOS technology with high mobility channel materials, specifically Ge for pMOS and III-V materials for nMOS, was the aim of the European Union FP7 funded Duallogic consortium, of which this project was part. The experimental work at the University of Glasgow was the III-V compound semiconductor MOSFET, in particular the study of Si processing compatible source/drain contacts to III-V MOSFET devices with InxGa1-xAs channel materials, which was an important aspect of this thesis. Another area investigated in this thesis is the impact of current crowding effects on source/drain contact resistance by aggressive scaling of devices. During this thesis, optimisation of a PdGe-based ohmic contact to buried channel device material with a In0.75GaAs channel led to a contact resistance of 0.15Ohm.mm compared to 1Ohm.mm in previous work by R. Hill. The PdGe-based contact also proved to be scalable in both vertical and lateral dimensions. This scaled structure was then integrated in a surface channel MOSFET device with 1μm access regions and gate lengths varying from 100nm to 20μm. The performance of the devices with 20μm gate lengths was then compared to devices with a NiGeAu based ohmic contact. An increase in RC, 1.82Ohm.mm vs. 0.94Ohm.mm, and Ron, 11.1Ohm.mm vs. 8.55Ohm.mm, was observed in the PdGe-based contact, which resulted in a decrease in gm, 92.3mS/mm vs. 103mS/mm, and Id,sat, 103mA/mm vs. 122mA/mm. However, further optimisation of the PdGe-based ohmic contact showed promising results with a contact resistance of 0.45Ohm.mm. The novel test structure is the first test structure, which makes direct contact to III-V material, with critical dimensions below the transfer length. This structure is able to experimentally observe the current crowding effects and allows for the extraction of the sheet resistance underneath the contact and a more accurate extraction of the specific contact resistivity. This offers a significant insight into the impact of the sheet resistance underneath the contact and the role it plays

    Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

    Get PDF
    The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies
    corecore