39 research outputs found
XNOR-VSH: A Valley-Spin Hall Effect-based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks
Binary neural networks (BNNs) have shown an immense promise for
resource-constrained edge artificial intelligence (AI) platforms as their
binarized weights and inputs can significantly reduce the compute, storage and
communication costs. Several works have explored XNOR-based BNNs using SRAMs
and nonvolatile memories (NVMs). However, these designs typically need two
bit-cells to encode signed weights leading to an area overhead. In this paper,
we address this issue by proposing a compact and low power in-memory computing
(IMC) of XNOR-based dot products featuring signed weight encoding in a single
bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer
tungsten di-selenide to design an XNOR bit-cell (named 'XNOR-VSH') with
differential storage and access-transistor-less topology. We co-optimize the
proposed VSH device and a memory array to enable robust in-memory dot product
computations between signed binary inputs and signed binary weights with sense
margin (SM) > 1 micro-amps. Our results show that the proposed XNOR-VSH array
achieves 4.8% ~ 9.0% and 37% ~ 63% lower IMC latency and energy, respectively,
with 4 % ~ 64% smaller area compared to spin-transfer-torque (STT)-MRAM and
spin-orbit-torque (SOT)-MRAM based XNOR-arrays
Valley-Spin Hall Effect-based Nonvolatile Memory with Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths
Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit
highly beneficial features for nonvolatile memory (NVM) design. Key advantages
of VSH-based magnetic random-access memory (VSH-MRAM) over spin orbit torque
(SOT)-MRAM include access transistor-less compact bit-cell and low power
switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless,
large device resistance in the read path (RS) due to low mobility of WSe2 and
Schottky contacts deteriorates sense margin, offsetting the benefits of
VSH-MRAM. To address this limitation, we propose another flavor of VSH-based
MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower RS
in the read path by electrically isolating the read and write terminals. This
is enabled by coupling VSH with electrically-isolated but magnetically-coupled
PMA magnets via interlayer exchange-coupling. Designing the proposed devices
using object oriented micro magnetic framework (OOMMF) simulation, we ensure
the robustness of the exchange-coupled PMA system under process variations. To
maintain a compact memory footprint, we share the read access transistor across
multiple bit-cells. Compared to the existing VSH-MRAMs, our design achieves
39%-42% and 36%-46% reduction in read time and energy, respectively, along with
1.1X-1.3X larger sense margin at a comparable area. This comes at the cost of
1.7X and 2.0X increase in write time and energy, respectively. Thus, the
proposed design is suitable for applications in which reads are more dominant
than writes
The 2020 magnetism roadmap
Following the success and relevance of the 2014 and 2017 Magnetism Roadmap articles, this 2020 Magnetism Roadmap edition takes yet another timely look at newly relevant and highly active areas in magnetism research. The overall layout of this article is unchanged, given that it has proved the most appropriate way to convey the most relevant aspects of today's magnetism research in a wide variety of sub-fields to a broad readership. A different group of experts has again been selected for this article, representing both the breadth of new research areas, and the desire to incorporate different voices and viewpoints. The latter is especially relevant for thistype of article, in which one's field of expertise has to be accommodated on two printed pages only, so that personal selection preferences are naturally rather more visible than in other types of articles. Most importantly, the very relevant advances in the field of magnetism research in recent years make the publication of yet another Magnetism Roadmap a very sensible and timely endeavour, allowing its authors and readers to take another broad-based, but concise look at the most significant developments in magnetism, their precise status, their challenges, and their anticipated future developments. While many of the contributions in this 2020 Magnetism Roadmap edition have significant associations with different aspects of magnetism, the general layout can nonetheless be classified in terms of three main themes: (i) phenomena, (ii) materials and characterization, and (iii) applications and devices. While these categories are unsurprisingly rather similar to the 2017 Roadmap, the order is different, in that the 2020 Roadmap considers phenomena first, even if their occurrences are naturally very difficult to separate from the materials exhibiting such phenomena. Nonetheless, the specifically selected topics seemed to be best displayed in the order presented here, in particular, because many of the phenomena or geometries discussed in (i) can be found or designed into a large variety of materials, so that the progression of the article embarks from more general concepts to more specific classes of materials in the selected order. Given that applications and devices are based on both phenomena and materials, it seemed most appropriate to close the article with the application and devices section (iii) once again. The 2020 Magnetism Roadmap article contains 14 sections, all of which were written by individual authors and experts, specifically addressing a subject in terms of its status, advances, challenges and perspectives in just two pages. Evidently, this two-page format limits the depth to which each subject can be described. Nonetheless, the most relevant and key aspects of each field are touched upon, which enables the Roadmap as whole to give its readership an initial overview of and outlook into a wide variety of topics and fields in a fairly condensed format. Correspondingly, the Roadmap pursues the goal of giving each reader a brief reference frame of relevant and current topics in modern applied magnetism research, even if not all sub-fields can be represented here. The first block of this 2020 Magnetism Roadmap, which is focussed on (i) phenomena, contains five contributions, which address the areas of interfacial Dzyaloshinskii-Moriya interactions, and two-dimensional and curvilinear magnetism, as well as spin-orbit torque phenomena and all optical magnetization reversal.
All of these contributions describe cutting edge aspects of rather fundamental physical processes and properties, associated with new and improved magnetic materials' properties, together with potential developments in terms of future devices and technology. As such, they form part of a widening magnetism 'phenomena reservoir' for utilization in applied magnetism and related device technology. The final block (iii) of this article focuses on such applications and device-related fields in four contributions relating to currently active areas of research, which are of course utilizing magnetic phenomena to enable specific functions. These contributions highlight the role of magnetism or spintronics in the field of neuromorphic and reservoir computing, terahertz technology, and domain wall-based logic. One aspect common to all of these application-related contributions is that they are not yet being utilized in commercially available technology; it is currently still an open question, whether or not such technological applications will be magnetism-based at all in the future, or if other types of materials and phenomena will yet outperform magnetism. This last point is actually a very good indication of the vibrancy of applied magnetism research today, given that it demonstrates that magnetism research is able to venture into novel application fields, based upon its portfolio of phenomena, effects and materials. This materials portfolio in particular defines the central block (ii) of this article, with its five contributions interconnecting phenomena with devices, for which materials and the characterization of their properties is the decisive discriminator between purely academically interesting aspects and the true viability of real-life devices, because only available materials and their associated fabrication and characterization methods permit reliable technological implementation. These five contributions specifically address magnetic films and multiferroic heterostructures for the purpose of spin electronic utilization, multi-scale materials modelling, and magnetic materials design based upon machine-learning, as well as materials characterization via polarized neutron measurements. As such, these contributions illustrate the balanced relevance of research into experimental and modelling magnetic materials, as well the importance of sophisticated characterization methods that allow for an ever-more refined understanding of materials. As a combined and integrated article, this 2020 Magnetism Roadmap is intended to be a reference point for current, novel and emerging research directions in modern magnetism, just as its 2014 and 2017 predecessors have been in previous years
FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks
Convolutional Neural Networks (CNNs) demonstrate excellent performance in
various applications but have high computational complexity. Quantization is
applied to reduce the latency and storage cost of CNNs. Among the quantization
methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique
advantage over 8-bit and 4-bit quantization. They replace the multiplication
operations in CNNs with additions, which are favoured on In-Memory-Computing
(IMC) devices. IMC acceleration for BWNs has been widely studied. However,
though TWNs have higher accuracy and better sparsity than BWNs, IMC
acceleration for TWNs has limited research. TWNs on existing IMC devices are
inefficient because the sparsity is not well utilized, and the addition
operation is not efficient.
In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we
propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to
skip the null operations on zero weights. Second, we propose a fast addition
scheme based on the memory Sense Amplifier to avoid the time overhead of both
carry propagation and writing back the carry to memory cells. Third, we further
propose a Combined-Stationary data mapping to reduce the data movement of
activations and weights and increase the parallelism across memory columns.
Simulation results show that for addition operations at the Sense Amplifier
level, FAT achieves 2.00X speedup, 1.22X power efficiency, and 1.22X area
efficiency compared with a State-Of-The-Art IMC accelerator ParaPIM. FAT
achieves 10.02X speedup and 12.19X energy efficiency compared with ParaPIM on
networks with 80% average sparsity.Comment: 14 page
Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS
Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop.
Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes.
With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor
Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs
One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories
CARRIER TRANSPORT IN DIRAC-BAND MATERIALS AND THEIR DEVICE PHYSICS
Ph.DDOCTOR OF PHILOSOPH
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Novel Computing Paradigms using Oscillators
This dissertation is concerned with new ways of using oscillators to perform computational tasks. Specifically, it introduces methods for building finite state machines (for general-purpose Boolean computation) as well as Ising machines (for solving combinatorial optimization problems) using coupled oscillator networks.But firstly, why oscillators? Why use them for computation?An important reason is simply that oscillators are fascinating. Coupled oscillator systems often display intriguing synchronization phenomena where spontaneous patterns arise. From the synchronous flashing of fireflies to Huygens' clocks ticking in unison, from the molecular mechanism of circadian rhythms to the phase patterns in oscillatory neural circuits, the observation and study of synchronization in coupled oscillators has a long and rich history. Engineers across many disciplines have also taken inspiration from these phenomena, e.g., to design high-performance radio frequency communication circuits and optical lasers. To be able to contribute to the study of coupled oscillators and leverage them in novel paradigms of computing is without question an interesting andfulfilling quest in and of itself.Moreover, as Moore's Law nears its limits, new computing paradigms that are different from mere conventional complementary metal–oxide–semiconductor (CMOS) scaling have become an important area of exploration. One broad direction aims to improve CMOS performance using device technology such as fin field-effect transistors (FinFET) and gate-all-around (GAA) FETs. Other new computing schemes are based on non-CMOS material and device technology, e.g., graphene, carbon nanotubes, memristive devices, optical devices, etc.. Another growing trend in both academia and industry is to build digital application-specific integrated circuits (ASIC) suitable for speeding up certain computational tasks, often leveraging the parallel nature of unconventional non-von Neumann architectures. These schemes seek to circumvent the limitations posed at the device level through innovations at the system/architecture level.Our work on oscillator-based computation represents a direction that is different from the above and features several points of novelty and attractiveness. Firstly, it makes meaningful use of nonlinear dynamical phenomena to tackle well-defined computational tasks that span analog and digital domains. It also differs from conventional computational systems at the fundamental logic encoding level, using timing/phase of oscillation as opposed to voltage levels to represent logic values. These differences bring about several advantages. The change of logic encoding scheme has several device- and system-level benefits related to noise immunity and interference resistance. The use of nonlinear oscillator dynamics allows our systems to address problems difficult for conventional digital computation. Furthermore, our schemes are amenable to realizations using almost all types of oscillators, allowing a wide variety of devices from multiple physical domains to serve as the substrate for computing. This ability to leverage emerging multiphysics devices need not put off the realization of our ideas far into the future. Instead, implementations using well-established circuit technology are already both practical and attractive.This work also differs from all past work on oscillator-based computing, which mostly focuses on specialized image preprocessing tasks, such as edge detection, image segmentation and pattern recognition. Perhaps its most unique feature is that our systems use transitions between analog and digital modes of operation --- unlike other existing schemes that simply couple oscillators and let their phases settle to a continuum of values, we use a special type of injection locking to make each oscillator settle to one of the several well-defined multistable phase-locked states, which we use to encode logic values for computation. Our schemes of oscillator-based Boolean and Ising computation are built upon this digitization of phase; they expand the scope of oscillator-based computing significantly.Our ideas are built on years of past research in the modelling, simulation and analysis of oscillators. While there is a considerable amount of literature (arguably since Christiaan Huygens wrote about his observation of synchronized pendulum clocks in the 17th century) analyzing the synchronization phenomenon from different perspectives at different levels, we have been able to further develop the theory of injection locking, connecting the dots to find a path of analysis that starts from the low-level differential equations of individual oscillators and arrives at phase-based models and energy landscapes of coupled oscillator systems. This theoretical scaffolding is able not only to explain the operation of oscillator-based systems, but also to serve as the basis for simulation and design tools. Building on this, we explore the practical design of our proposed systems, demonstrate working prototypes, as well as develop the techniques, tools and methodologies essential for the process
Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems
We present the science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems, targeting an evolution in technology, that might lead to impacts and benefits reaching into most areas of society. This roadmap was developed within the framework of the European Graphene Flagship and outlines the main targets and research areas as best understood at the start of this ambitious project. We provide an overview of the key aspects of graphene and related materials (GRMs), ranging from fundamental research challenges to a variety of applications in a large number of sectors, highlighting the steps necessary to take GRMs from a state of raw potential to a point where they might revolutionize multiple industries. We also define an extensive list of acronyms in an effort to standardize the nomenclature in this emerging field.Peer ReviewedPostprint (published version
ULTRARAM™:Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays
In this thesis, a novel memory based on III-V compound semiconductors is studied, both theoretically and experimentally, with the aim of developing a technology with superior performance capabilities to established and emerging rival memories. This technology is known as ULTRARAM™. The memory concept is based on quantum resonant tunnelling through InAs/AlSb heterostructures, which are engineered to only allow electron tunnelling at precise energy alignment(s) when a bias is applied. The memory device features a floating gate (FG) as the storage medium, where electrons that tunnel through the InAs/AlSb heterostructure are confined in the FG to define the memory logic (0 or 1). The large conduction band offset of the InAs/AlSb heterojunction (2.1 eV) keeps electrons in the FG indefinitely, constituting a non-volatile logic state. Electrons can be removed from the FG via a similar resonant tunnelling process by reversing the voltage polarity. This concept shares similarities with flash memory, however the resonant tunnelling mechanism provides ultra-low-power, low-voltage, high-endurance and high-speed switching capability. The quantum tunnelling junction is studied in detail using the non-equilibrium Green’s function (NEGF) method. Then, Poisson-Schrödinger simulations are used to design a high-contrast readout procedure for the memory using the unusual type-III band-offset of the InAs/GaSb heterojunction. With the theoretical groundwork for the technology laid out, the memory performance is modelled and a high-density ULTRARAM™ memory architecture is proposed for random-access memory applications. Later, NEGF calculations are used for a detailed study of the process tolerances in the tunnelling region required for ULTRARAM™ large-scale wafer manufacture. Using interfacial misfit array growth techniques, III-V layers (InAs, AlSb and GaSb) for ULTRARAM™ were successfully implemented on both GaAs and Si substrates. Single devices and 2×2 arrays were then fabricated using a top-down processing approach. The memories demonstrated outstanding memory performance on both substrate materials at 10, 20 and 50 µm gate lengths at room temperature. Non-volatile switching was obtained with ≤ 2.5 V pulses, corresponding to a switching energy per unit area that is lower than DRAM and flash by factors of 100 and 1000 respectively. Memory logic was retained for over 24 hours whilst undergoing over 10^6 readout operations. Analysis of the retention data suggests a storage time exceeding 1000 years. Devices showed promising durability results, enduring over 10^7 cycles without degradation, at least two orders of magnitude improvement over flash memory. Switching of the cell’s logic was possible at 500 µs pulse durations for a 20 µm gate length, suggesting a subns switching time if scaled to modern-day feature sizes. The proposed half-voltage architecture is shown to operate in principle, where the memory state is preserved during a disturbance test of > 10^5 half-cycles. With regard to the device physics, these findings point towards ULTRARAM™ as a universal memory candidate. The path towards future commercial viability relies on process development for aggressive device and array-size scaling and implementation on larger Si wafe