Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

An investigation into adaptive power reduction techniques for neural hardware

In light of the growing applicability of Artificial Neural Network (ANN) in the signal processing field [1] and the present thrust of the semiconductor industry towards lowpower SOCs for mobile devices [2], the power consumption of ANN hardware has become a very important implementation issue. Adaptability is a powerful and useful feature of neural networks. All current approaches for low-power ANN hardware techniques are ‘non-adaptive’ with respect to the power consumption of the network (i.e. power-reduction is not an objective of the adaptation/learning process). In the research work presented in this thesis, investigations on possible adaptive power reduction techniques have been carried out, which attempt to exploit the adaptability of neural networks in order to reduce the power consumption. Three separate approaches for such adaptive power reduction are proposed: adaptation of size, adaptation of network weights and adaptation of calculation precision. Initial case studies exhibit promising results with significantpower reduction

Hierarchical Associative Memory Based on Oscillatory Neural Network

In this thesis we explore algorithms and develop architectures based on emerging nano-device technologies for cognitive computing tasks such as recognition, classification, and vision. In particular we focus on pattern matching in high dimensional vector spaces to address the nearest neighbor search problem. Recent progress in nanotechnology provides us novel nano-devices with special nonlinear response characteristics that fit cognitive tasks better than general purpose computing. We build an associative memory (AM) by weakly coupling nano-oscillators as an oscillatory neural network and design a hierarchical tree structure to organize groups of AM units. For hierarchical recognition, we first examine an architecture where image patterns are partitioned into different receptive fields and processed by individual AM units in lower levels, and then abstracted using sparse coding techniques for recognition at higher levels. A second tree structure model is developed as a more scalable AM architecture for large data sets. In this model, patterns are classified by hierarchical k-means clustering and organized in hierarchical clusters. Then the recognition process is done by comparison between the input patterns and centroids identified in the clustering process. The tree is explored in a "depth-only" manner until the closest image pattern is output. We also extend this search technique to incorporate a branch-and-bound algorithm. The models and corresponding algorithms are tested on two standard face recognition data-sets. We show that the depth-only hierarchical model is very data-set dependent and performs with 97% or 67% recognition when compared to a single large associative memory, while the branch and bound search increases time by only a factor of two compared to the depth-only search

Roadmap on semiconductor-cell biointerfaces.

This roadmap outlines the role semiconductor-based materials play in understanding the complex biophysical dynamics at multiple length scales, as well as the design and implementation of next-generation electronic, optoelectronic, and mechanical devices for biointerfaces. The roadmap emphasizes the advantages of semiconductor building blocks in interfacing, monitoring, and manipulating the activity of biological components, and discusses the possibility of using active semiconductor-cell interfaces for discovering new signaling processes in the biological world

Integrated Application of Active Controls (IAAC) technology to an advanced subsonic transport project: Current and advanced act control system definition study. Volume 2: Appendices

The current status of the Active Controls Technology (ACT) for the advanced subsonic transport project is investigated through analysis of the systems technical data. Control systems technologies under examination include computerized reliability analysis, pitch axis fly by wire actuator, flaperon actuation system design trade study, control law synthesis and analysis, flutter mode control and gust load alleviation analysis, and implementation of alternative ACT systems. Extensive analysis of the computer techniques involved in each system is included

Large-scale, high-density (up to 512 channels) recording of local circuits in behaving animals

Monitoring representative fractions of neurons from multiple brain circuits in behaving animals is necessary for understanding neuronal computation. Here we describe a system that allows high channel count recordings from a small volume of neuronal tissue using a lightweight signal multiplexing head-stage that permits free behavior of small rodents. The system integrates multi-shank, high-density recording silicon probes, ultra-flexible interconnects and a miniaturized microdrive. These improvements allowed for simultaneous recordings of local field potentials and unit activity from hundreds of sites without confining free movements of the animal. The advantages of large-scale recordings are illustrated by determining the electro-anatomical boundaries of layers and regions in the hippocampus and neocortex and constructing a circuit diagram of functional connections among neurons in real anatomical space. These methods will allow the investigation of circuit operations and behavior-dependent inter-regional interactions for testing hypotheses of neural networks and brain function

Full-wave analysis of large conductor systems over substrate

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaves 137-145).Designers of high-performance integrated circuits are paying ever-increasing attention to minimizing problems associated with interconnects such as noise, signal delay, crosstalk, etc., many of which are caused by the presence of a conductive substrate. The severity of these problems increases as integrated circuit clock frequencies rise into the multiple gigahertz range. In this thesis, a simulation tool is presented for the extraction of full-wave interconnect impedances in the presence of a conducting substrate. The substrate effects are accounted for through the use of full-wave layered Green's functions in a mixed-potential integral equation (MPIE) formulation. Particularly, the choice of implementation for the layered Green's function kernels motivates the development of accelerated techniques for both their 3D volume and 2D surface integrations, where each integration type can be reduced to a sum of D line integrals. In addition, a set of high-order, frequency-independent basis functions is developed with the ability to parameterize the frequency-dependent nature of the solution space, hence reducing the number of unknowns required to capture the interconnects' frequency-variant behavior.(cont.) Moreover, a pre-corrected FFT acceleration technique, conventional for the treatment of scalar Green's function kernels, is extended in the solver to accommodate the dyadic Green's function kernels encountered in the substrate modeling problem. Overall, the integral-equation solver, combined with its numerous acceleration techniques, serves as a viable solution to full-wave substrate impedance extractions of large and complex interconnect structures.by Xin Hu.Ph.D

Low Power Resonant Rotary Global Clock Distribution Network Design

Along with the increasing complexity of the modern very large scale integrated (VLSI) circuit design, the power consumption of the clock distribution network in digital integrated circuits is continuously increasing. In terms of power and clock skew, the resonant clock distribution network has been studied as a promising alternative to the conventional clock distribution network. Resonant clock distribution network, which works based on adiabatic switching principles, provides a complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous VLSI circuits.This dissertation work aims to develop the global clock distribution network for one kind of resonant clocking technologies: The resonant rotary clocking technology. The following critical aspects are addressed in this work: (1) A novel rotary oscillator array (ROA) topology is proposed to solve the signal rotation direction uniformity problem, in order to support the design of resonant rotary clocking based low-skew clock distribution network; (2) A synchronization scheme is proposed to solve the large scale rotary clocking generation circuit synchronization problem; (3) A low-skew rotary clock distribution network design methodology is proposed with frequency, power and skew optimizations; (4) A resonant rotary clocking based physical design flow is proposed, which can be integrated in the current mainstream IC design flow; (5) A dynamic rotary frequency divider is proposed for dynamic frequency scaling applications. Experimental and theoretical results show: (1) The efficiency of the proposed methodology in the construction of low-skew, low-power resonant rotary clock distribution network. (2) The effectiveness of the dynamic rotary frequency divider in extending the operating frequency range of the low-power resonant rotary based applications.Ph.D., Electrical Engineering -- Drexel University, 201

Through-wafer interrogation of MEMS device motion

Microelectromechanical systems (MEMS) have been the focus of many research groups because of their wide variety of uses in sensing and actuation applications. A fundamental barrier facing designers of next generation MEMS is the inability to access accurate, real-time microstructure positional information to determine if the device is performing as expected. Previously explored optical and electrical methods of MEMS device monitoring are often only suitable for research environments, or are unable to produce clear and meaningful characterization of device motion. The most desirable MEMS monitoring method would be one that could be implemented at the device level, which would allow the monitoring system to be fabricated along with the device itself. This research explores a through-wafer method of optically monitoring and characterizing the motion of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS). Positional monitoring results obtained from a 1.3 mum wavelength through-wafer optical probe are presented, as well as a method of device level implementation of the monitoring system