VLSI implementation of an energy-aware wake-up detector for an acoustic surveillance sensor network

We present a low-power VLSI wake-up detector for a sensor network that uses acoustic signals to localize ground-base vehicles. The detection criterion is the degree of low-frequency periodicity in the acoustic signal, and the periodicity is computed from the "bumpiness" of the autocorrelation of a one-bit version of the signal. We then describe a CMOS ASIC that implements the periodicity estimation algorithm. The ASIC is functional and its core consumes 835 nanowatts. It was integrated into an acoustic enclosure and deployed in field tests with synthesized sounds and ground-based vehicles.Fil: Goldberg, David H.. Johns Hopkins University; Estados UnidosFil: Andreou, Andreas. Johns Hopkins University; Estados UnidosFil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; ArgentinaFil: Pouliquen, Philippe O.. Johns Hopkins University; Estados UnidosFil: Riddle, Laurence. Signal Systems Corporation; Estados UnidosFil: Rosasco, Rich. Signal Systems Corporation; Estados Unido

Effects of Bulk and Surface Conductivity on the Performance of CdZnTe Pixel Detectors

We studied the effects of bulk and surface conductivity on the performance of high-resistivity CdZnTe (CZT) pixel detectors with Pt contacts. We emphasize the difference in mechanisms of the bulk and surface conductivity as indicated by their different temperature behaviors. In addition, the existence of a thin (10-100 A) oxide layer on the surface of CZT, formed during the fabrication process, affects both bulk and surface leakage currents. We demonstrate that the measured I-V dependencies of bulk current can be explained by considering the CZT detector as a metal-semiconductor-metal system with two back-to-back Schottky-barrier contacts. The high surface leakage current is apparently due to the presence of a low-resistivity surface layer that has characteristics which differ considerably from those of the bulk material. This surface layer has a profound effect on the charge collection efficiency in detectors with multi-contact geometry; some fraction of the electric field lines originated on the cathode intersects the surface areas between the pixel contacts where the charge produced by an ionizing particle gets trapped. To overcome this effect we place a grid of thin electrodes between the pixel contacts; when the grid is negatively biased, the strong electric field in the gaps between the pixels forces the electrons landing on the surface to move toward the contacts, preventing the charge loss. We have investigated these effects by using CZT pixel detectors indium bump bonded to a custom-built VLSI readout chip

Fault Secure Encoder and Decoder for NanoMemory Applications

Memory cells have been protected from soft errors for more than a decade; due to the increase in soft error rate in logic circuits, the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and must also be protected. We introduce a new approach to design fault-secure encoder and decoder circuitry for memory designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes whose redundancy makes the design of fault-secure detectors (FSD) particularly simple. We further quantify the importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder. We prove that Euclidean geometry low-density parity-check (EG-LDPC) codes have the fault-secure detector capability. Using some of the smaller EG-LDPC codes, we can tolerate bit or nanowire defect rates of 10% and fault rates of 10^(-18) upsets/device/cycle, achieving a FIT rate at or below one for the entire memory system and a memory density of 10^(11) bit/cm^2 with nanowire pitch of 10 nm for memory blocks of 10 Mb or larger. Larger EG-LDPC codes can achieve even higher reliability and lower area overhead

A silicon implementation of the fly's optomotor control system

Flies are capable of stabilizing their body during free flight by using visual motion information to estimate self-rotation. We have built a hardware model of this optomotor control system in a standard CMOS VLSI process. The result is a small, low-power chip that receives input directly from the real world through on-board photoreceptors and generates motor commands in real time. The chip was tested under closed-loop conditions typically used for insect studies. The silicon system exhibited stable control sufficiently analogous to the biological system to allow for quantitative comparisons

A Pixel Vertex Tracker for the TESLA Detector

In order to fully exploit the physics potential of a e+e- linear collider, such as TESLA, a Vertex Tracker providing high resolution track reconstruction is required. Hybrid Silicon pixel sensors are an attractive sensor technology option due to their read-out speed and radiation hardness, favoured in the high rate TESLA environment, but have been so far limited by the achievable single point space resolution. A novel layout of pixel detectors with interleaved cells to improve their spatial resolution is introduced and the results of the characterisation of a first set of test structures are discussed. In this note, a conceptual design of the TESLA Vertex Tracker, based on hybrid pixel sensors is presentedComment: 20 pages, 11 figure

A Novel Optical/digital Processing System for Pattern Recognition

This paper describes two processing algorithms that can be implemented optically: the Radon transform and angular correlation. These two algorithms can be combined in one optical processor to extract all the basic geometric and amplitude features from objects embedded in video imagery. We show that the internal amplitude structure of objects is recovered by the Radon transform, which is a well-known result, but, in addition, we show simulation results that calculate angular correlation, a simple but unique algorithm that extracts object boundaries from suitably threshold images from which length, width, area, aspect ratio, and orientation can be derived. In addition to circumventing scale and rotation distortions, these simulations indicate that the features derived from the angular correlation algorithm are relatively insensitive to tracking shifts and image noise. Some optical architecture concepts, including one based on micro-optical lenslet arrays, have been developed to implement these algorithms. Simulation test and evaluation using simple synthetic object data will be described, including results of a study that uses object boundaries (derivable from angular correlation) to classify simple objects using a neural network

Performance of a Low Noise Front-end ASIC for Si/CdTe Detectors in Compton Gamma-ray Telescope

Compton telescopes based on semiconductor technologies are being developed to explore the gamma-ray universe in an energy band 0.1--20 MeV, which is not well covered by the present or near-future gamma-ray telescopes. The key feature of such Compton telescopes is the high energy resolution that is crucial for high angular resolution and high background rejection capability. The energy resolution around 1 keV is required to approach physical limit of the angular resolution due to Doppler broadening. We have developed a low noise front-end ASIC (Application-Specific Integrated Circuit), VA32TA, to realize this goal for the readout of Double-sided Silicon Strip Detector (DSSD) and Cadmium Telluride (CdTe) pixel detector which are essential elements of the semiconductor Compton telescope. We report on the design and test results of the VA32TA. We have reached an energy resolution of 1.3 keV (FWHM) for 60 keV and 122 keV at 0 degree C with a DSSD and 1.7 keV (FWHM) with a CdTe detector.Comment: 6 pages, 7 figures, IEEE style file, to appear in IEEE Trans. Nucl. Sc