30 research outputs found

    Computer vision algorithms on reconfigurable logic arrays

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    On-line recognition of English and numerical characters.

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    by Cheung Wai-Hung Wellis.Thesis (M.Sc.)--Chinese University of Hong Kong, 1992.Includes bibliographical references (leaves 52-54).ACKNOWLEDGEMENTSABSTRACTChapter 1 --- INTRODUCTION --- p.1Chapter 1.1 --- CLASSIFICATION OF CHARACTER RECOGNITION --- p.1Chapter 1.2 --- HISTORICAL DEVELOPMENT --- p.3Chapter 1.3 --- RECOGNITION METHODOLOGY --- p.4Chapter 2 --- ORGANIZATION OF THIS REPORT --- p.7Chapter 3 --- DATA SAMPLING --- p.8Chapter 3.1 --- GENERAL CONSIDERATION --- p.8Chapter 3.2 --- IMPLEMENTATION --- p.9Chapter 4 --- PREPROCESSING --- p.10Chapter 4.1 --- GENERAL CONSIDERATION --- p.10Chapter 4.2 --- IMPLEMENTATION --- p.12Chapter 4.2.1 --- Stroke connection --- p.12Chapter 4.2.2 --- Rotation --- p.12Chapter 4.2.3 --- Scaling --- p.14Chapter 4.2.4 --- De-skewing --- p.15Chapter 5 --- STROKE SEGMENTATION --- p.17Chapter 5.1 --- CONSIDERATION --- p.17Chapter 5.2 --- IMPLEMENTATION --- p.20Chapter 6 --- LEARNING --- p.26Chapter 7 --- PROTOTYPE MANAGEMENT --- p.27Chapter 8 --- RECOGNITION --- p.29Chapter 8.1 --- CONSIDERATION --- p.29Chapter 8.1.1 --- Delayed Stroke Tagging --- p.29Chapter 8.1.2 --- Bi-gram --- p.29Chapter 8.1.3 --- Character Scoring --- p.30Chapter 8.1.4 --- Ligature Handling --- p.32Chapter 8.1.5 --- Word Scoring --- p.32Chapter 8.2 --- IMPLEMENTATION --- p.33Chapter 8.2.1 --- Simple Matching --- p.33Chapter 8.2.2 --- Best First Search Matching --- p.33Chapter 8.2.3 --- Multiple Track Method --- p.35Chapter 8.3 --- SYSTEM PERFORMANCE TUNING --- p.37Chapter 9 --- POST-PROCESSING --- p.38Chapter 9.1 --- PROBABILITY MODEL --- p.38Chapter 9.2 --- WORD DICTIONARY APPROACH --- p.39Chapter 10 --- SYSTEM IMPLEMENTATION AND PERFORMANCE --- p.41Chapter 11 --- DISCUSSION --- p.43Chapter 12 --- EPILOG --- p.47Chapter APPENDIX I - --- PROBLEMS ENCOUNTERED AND SUGGESTED ENHANCEMENTS ON THE SYSTEM --- p.48Chapter APPENDIX II - --- GLOSSARIES --- p.51REFERENCES --- p.5

    Pulse stream VLSI circuits and techniques for the implementation of neural networks

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    Visual inspection : image sampling, algorithms and architectures

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    The thesis concerns the hexagonal sampling of images, the processing of industrially derived images, and the design of a novel processor element that can be assembled into pipelines to effect fast, economic and reliable processing. A hexagonally sampled two dimensional image can require 13.4% fewer sampling points than a square sampled equivalent. The grid symmetry results in simpler processing operators that compute more efficiently than square grid operators. Computation savings approaching 44% arc demonstrated. New hexagonal operators arc reported including a Gaussian smoothing filter, a binary thinner, and an edge detector with comparable accuracy to that of the Sobel detector. The design of hexagonal arrays of sensors is considered. Operators requiring small local areas of support are shown to be sufficient for processing controlled lighting and industrial images. Case studies show that small features in hexagonally processed images maintain their shape better, and that processes can tolerate a lower signal to noise ratio, than that for equivalent square processed images. The modelling of small defects in surfaces has been studied in depth. The flexible programmable processor element can perform the low level local operators required for industrial image processing on both square and hexagonal grids. The element has been specified and simulated by a high level computer program. A fast communication channel allows for dynamic reprogramming by a control computer, and the video rate element can be assembled into various pipeline architectures, that may eventually be adaptively controlled

    Parallelizing Feed-Forward Artificial Neural Networks on Transputers

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    This thesis is about parallelizing the training phase of a feed-forward, artificial neural network. More specifically, we develop and analyze a number of parallelizations of the widely used neural net learning algorithm called back-propagation. We describe two different strategies for parallelizing the back-propagation algorithm. A number of parallelizations employing these strategies have been implemented on a system of 48 transputers, permitting us to evaluate and analyze their performances based on the results of actual runs

    Fundamentals

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    Volume 1 establishes the foundations of this new field. It goes through all the steps from data collection, their summary and clustering, to different aspects of resource-aware learning, i.e., hardware, memory, energy, and communication awareness. Machine learning methods are inspected with respect to resource requirements and how to enhance scalability on diverse computing architectures ranging from embedded systems to large computing clusters
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