Design and implementation of DA FIR filter for bio-inspired computing architecture

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability

Efficient Digital Signal Processing Techniques and Architectures for On-Board Processors

In this paper, we present a number of algorithmic and architectural DSP solutions to be incorporated in digital OBPs for communication satellites to boost the system performance primarily in terms of reducing their power consumption. More specifically this article addresses (1) Infinite impulse response (IIR) implementation of digital filters, (2) Efficiency savings in channeliser FFT twiddle storage and multiplications and their reconfigurable implementation (3) Companding of interconnect data, and (4) Critically sampled/reduced over-sampling channelisation. The applicability and efficiency of these approaches were evaluated in detail during our European Space Agency (ESA) funded research project entitled "Efficient Techniques for On-Board Processing”, undertaken by Airbus Defence and Space and the Applied DSP and VLSI Research Group at the University of Westminster. The results demonstrated noteworthy improvements both in terms of power dissipation, and furthermore in the reduction of circuit complexity for future digital OBPs, which will be shown at the summary of results section

Mixed-Signal Neural Network Implementation with Programmable Neuron

This thesis introduces implementation of mixed-signal building blocks of an artificial neural network; namely the neuron and the synaptic multiplier. This thesis, also, investigates the nonlinear dynamic behavior of a single artificial neuron and presents a Distributed Arithmetic (DA)-based Finite Impulse Response (FIR) filter. All the introduced structures are designed and custom laid out

A 36 µW 1.1 mm2 reconfigurable analog front-end for cardiovascular and respiratory signals recording

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksThis paper presents a 1.2 V 36 µW reconfigurable analog front-end (R-AFE) as a general-purpose low-cost IC for multiple-mode biomedical signals acquisition. The R-AFE efficiently reuses a reconfigurable preamplifier, a current generator (CG), and a mixed signal processing unit, having an area of 1.1 mm2 per R-AFE while supporting five acquisition modes to record different forms of cardiovascular and respiratory signals. The R-AFE can interface with voltage-, current-, impedance-, and light-sensors and hence can measure electrocardiography (ECG), bio-impedance (BioZ), photoplethysmogram (PPG), galvanic skin response (GSR), and general-purpose analog signals. Thanks to the chopper preamplifier and the low-noise CG utilizing dynamic element matching, the R-AFE mitigates 1/f noise from both the preamplifier and the CG for improved measurement sensitivity. The IC achieves competitive performance compared to the state-of-the-art dedicated readout ICs of ECG, BioZ, GSR, and PPG, but with approximately 1.4×-5.3× smaller chip area per channel.Peer ReviewedPostprint (author's final draft

Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

Optimal analog wavelet bases construction using hybrid optimization algorithm

An approach for the construction of optimal analog wavelet bases is presented. First, the definition of an analog wavelet is given. Based on the definition and the least-squares error criterion, a general framework for designing optimal analog wavelet bases is established, which is one of difficult nonlinear constrained optimization problems. Then, to solve this problem, a hybrid algorithm by combining chaotic map particle swarm optimization (CPSO) with local sequential quadratic programming (SQP) is proposed. CPSO is an improved PSO in which the saw tooth chaotic map is used to raise its global search ability. CPSO is a global optimizer to search the estimates of the global solution, while the SQP is employed for the local search and refining the estimates. Benefiting from good global search ability of CPSO and powerful local search ability of SQP, a high-precision global optimum in this problem can be gained. Finally, a series of optimal analog wavelet bases are constructed using the hybrid algorithm. The proposed method is tested for various wavelet bases and the improved performance is compared with previous works.Peer reviewedFinal Published versio