284 research outputs found
Satisfiability Modulo Theory based Methodology for Floorplanning in VLSI Circuits
This paper proposes a Satisfiability Modulo Theory based formulation for
floorplanning in VLSI circuits. The proposed approach allows a number of fixed
blocks to be placed within a layout region without overlapping and at the same
time minimizing the area of the layout region. The proposed approach is
extended to allow a number of fixed blocks with ability to rotate and flexible
blocks (with variable width and height) to be placed within a layout without
overlap. Our target in all cases is reduction in area occupied on a chip which
is of vital importance in obtaining a good circuit design. Satisfiability
Modulo Theory combines the problem of Boolean satisfiability with domains such
as convex optimization. Satisfiability Modulo Theory provides a richer modeling
language than is possible with pure Boolean SAT formulas. We have conducted our
experiments on MCNC and GSRC benchmark circuits to calculate the total area
occupied, amount of deadspace and the total CPU time consumed while placing the
blocks without overlapping. The results obtained shows clearly that the amount
of dead space or wasted space is reduced if rotation is applied to the blocks.Comment: 8 pages,5 figure
PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning
Floorplanning is the first stage of VLSI physical design. An effective
floorplanning engine definitely has positive impact on chip design speed,
quality and performance. In this paper, we present a novel mathematical model
to characterize non-overlapping of modules, and propose a flat fixed-outline
floorplanning algorithm based on the VLSI global placement approach using
Poisson's equation. The algorithm consists of global floorplanning and
legalization phases. In global floorplanning, we redefine the potential energy
of each module based on the novel mathematical model for characterizing
non-overlapping of modules and an analytical solution of Poisson's equation. In
this scheme, the widths of soft modules appear as variables in the energy
function and can be optimized. Moreover, we design a fast approximate
computation scheme for partial derivatives of the potential energy. In
legalization, based on the defined horizontal and vertical constraint graphs,
we eliminate overlaps between modules remained after global floorplanning, by
modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and
ami49\_x benchmarks show that, our algorithm improves the average wirelength by
at least 2\% and 5\% on small and large scale benchmarks with certain
whitespace, respectively, compared to state-of-the-art floorplanners
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A new partitioning approach for layout synthesis from register-transfer netlists
Most of the IC today are described and documented using heiarchical netlists. In addition to gates, latches, and flip-flops, these netlists include sliceable register-transfer components such as registers, counters, adders, ALUs, shifters, register files, and multiplexers. Usually, these components are decomposed into basic gates, latches, and flip-flops, and are laid out using standard cells. The standard cell architecture requires excessive routing area, and does not exploit the bit-sliced nature of register-transfer components. In this paper, we present a new sliced-layout architecture to alleviate the preceding problems. We also describe partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between blocks. This approach improves the overall area utilization and minimizes the total wire length
Floorplan-guided placement for large-scale mixed-size designs
In the nanometer scale era, placement has become an extremely challenging stage in modern Very-Large-Scale Integration (VLSI) designs. Millions of objects need to be placed legally within a chip region, while both the interconnection and object distribution have to be optimized simultaneously. Due to the extensive use of Intellectual Property (IP) and embedded memory blocks, a design usually contains tens or even hundreds of big macros. A design with big movable macros and numerous standard cells is known as mixed-size design. Due to the big size difference between big macros and standard cells, the placement of mixed-size designs is much more difficult than the standard-cell placement.
This work presents an efficient and high-quality placement tool to handle modern large-scale mixed-size designs. This tool is developed based on a new placement algorithm flow. The main idea is to use the fixed-outline floorplanning algorithm to guide the state-of-the-art analytical placer. This new flow consists of four steps: 1) The objects in the original netlist are clustered into blocks; 2) Floorplanning is performed on the blocks; 3) The blocks are shifted within the chip region to further optimize the wirelength; 4) With big macro locations fixed, incremental placement is applied to place the remaining objects. Several key techniques are proposed to be used in the first two steps. These techniques are mainly focused on the following two aspects: 1) Hypergraph clustering algorithm that can cut down the original problem size without loss of placement Quality of Results (QoR); 2) Fixed-outline floorplanning algorithm that can provide a good guidance to the analytical placer at the global level.
The effectiveness of each key technique is demonstrated by promising experimental results compared with the state-of-the-art algorithms. Moreover, using the industrial mixed-size designs, the new placement tool shows better performance than other existing approaches
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
3D IC optimal layout design. A parallel and distributed topological approach
The task of 3D ICs layout design involves the assembly of millions of
components taking into account many different requirements and constraints such
as topological, wiring or manufacturability ones. It is a NP-hard problem that
requires new non-deterministic and heuristic algorithms. Considering the time
complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is
superior to any other local search method. Nevertheless, it can often miss to
reach a quasi-optimal solution in 3D spaces. The presented approach uses an
original 3D layout graph partitioning heuristics implemented with use of the
extremal optimization method. The goal is to minimize the total wire-length in
the chip. In order to improve the time complexity a parallel and distributed
Java implementation is applied. Inside one Java Virtual Machine separate
optimization algorithms are executed by independent threads. The work may also
be shared among different machines by means of The Java Remote Method
Invocation system.Comment: 26 pages, 9 figure
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