Future benefits and applications of intelligent on-board processing to VSAT services

The trends and roles of VSAT services in the year 2010 time frame are examined based on an overall network and service model for that period. An estimate of the VSAT traffic is then made and the service and general network requirements are identified. In order to accommodate these traffic needs, four satellite VSAT architectures based on the use of fixed or scanning multibeam antennas in conjunction with IF switching or onboard regeneration and baseband processing are suggested. The performance of each of these architectures is assessed and the key enabling technologies are identified

Performance evaluation of currently available VLSI implementations satisfying U-interface requirements for an ISDN in South Africa.

A project report submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering.This project report examines the performance of three VLSI U-interface implementations satisfying the requirements of Basic Access on an ISDN. The systems evaluated are the Intel 89120,Siemens PEB2090 and STC DSP144, operating on 2BIQ, MMS4J and SU32 line codes respectively. Before evaluating the three abovementioned systems, a review of the underlying principles of U-interface technology is presented. Included in the review are aspects of transmission line theory, line coding, echo-cancellation, decision feedback equalisation, and pulse density modulation. The functional specifications of the three systems are then presented followed by a practical evaluation of each system. As an aid to testing the transmission systems, an evaluation board has been designed and built. The latter provides the necessary functionality to correctly activate each system, as well as the appropriate interfacing requirements for the error-rate tester. The U-interface transmission systems are evaluated on a number of test-loops, comprising sections of cable varying in length and gauge. Additionally, impairments are injected into data-carrying cables, in order to test the performance of each system in the presence of noise. The results of each test are recorded and analysed. Finally, a recommendation is made in favour of the 2BIQ U-interface. It is shown to offer superior transmission performance, at the expense of a slightly higher transmit-power level.Andrew Chakane 201

Visualizing three-dimensional graph drawings

viii, 110 leaves : ill. (some col.) ; 29 cm.The GLuskap system for interactive three-dimensional graph drawing applies techniques of scientific visualization and interactive systems to the construction, display, and analysis of graph drawings. Important features of the system include support for large-screen stereographic 3D display with immersive head-tracking and motion-tracked interactive 3D wand control. A distributed rendering architecture contributes to the portability of the system, with user control performed on a laptop computer without specialized graphics hardware. An interface for implementing graph drawing layout and analysis algorithms in the Python programming language is also provided. This thesis describes comprehensively the work on the system by the author—this work includes the design and implementation of the major features described above. Further directions for continued development and research in cognitive tools for graph drawing research are also suggested

X.25 traffic generator

Due to the lower cost and error free data transmission capabilities offered by packet switching, numerous countries have installed national packet switched networks. The South African packet network, SAPONET-P, became operational in 1982 and has been growing rapidly, creating a need for network test equipment. This thesis describes the design of a high speed traffic generator which can be used to test and monitor the throughput capabilities of equipment or part of the network as a whole. To meet the main requirement of the traffic generator, that it should support a number of high speed X.25 lines, a multiprocessor architecture was chosen to cope with the high data throughput. An IBM PC was used as the base system, with several specially designed X.25 cards being installed in its expansion slots. The major part of the work done was on the design and development of the X.25 cards, each of which provides two high speed (64 Kbps) X.25 links. In order to achieve this throughput, the card uses three processors coupled on a local bus to a 256K multi-port memory. Two WD25ll processors implement the link level of the X.25 packet switching protocol (LAPB), with the required software being micro-encoded on the chip. An 8088 processor, the same as is used in the PC, implements the packet level, the traffic generator and overall control of the card. Extensive use was made of programmable array logic (PAL) devices to implement the system logic required. All programs for the traffic generator are written in the modern and powerful c language which is ideally suited to the application. The software was written in a modular fashion with the various modules being linked together by means of a set of common data structures. Use was made of packet buffers and job queueing to allow the traffic generator to cope with very high peak data rates. As well as programs for the X.25 cards, a monitor program runs on the PC and allows the· user to view statistics screens and modify the traffic generator configuration. While primarily designed for the,traffic generator application, the X.25 card may also be configured for a variety of other networking applications. By substituting a local area network (LAN) processor for the X.25 one, the card can be used as a low cost network card or as a network file server. The card can also be configured to provide a low cost means of connecting a PC based workstation to the packet switching network. As all programs are downloaded onto the cards from the PC, it is relatively easy to modify or upgrade the software. Thus while meeting the original project requirements, the traffic generator design has a flexible and expandible nature

Operating System Support for Redundant Multithreading

Failing hardware is a fact and trends in microprocessor design indicate that the fraction of hardware suffering from permanent and transient faults will continue to increase in future chip generations. Researchers proposed various solutions to this issue with different downsides: Specialized hardware components make hardware more expensive in production and consume additional energy at runtime. Fault-tolerant algorithms and libraries enforce specific programming models on the developer. Compiler-based fault tolerance requires the source code for all applications to be available for recompilation. In this thesis I present ASTEROID, an operating system architecture that integrates applications with different reliability needs. ASTEROID is built on top of the L4/Fiasco.OC microkernel and extends the system with Romain, an operating system service that transparently replicates user applications. Romain supports single- and multi-threaded applications without requiring access to the application's source code. Romain replicates applications and their resources completely and thereby does not rely on hardware extensions, such as ECC-protected memory. In my thesis I describe how to efficiently implement replication as a form of redundant multithreading in software. I develop mechanisms to manage replica resources and to make multi-threaded programs behave deterministically for replication. I furthermore present an approach to handle applications that use shared-memory channels with other programs. My evaluation shows that Romain provides 100% error detection and more than 99.6% error correction for single-bit flips in memory and general-purpose registers. At the same time, Romain's execution time overhead is below 14% for single-threaded applications running in triple-modular redundant mode. The last part of my thesis acknowledges that software-implemented fault tolerance methods often rely on the correct functioning of a certain set of hardware and software components, the Reliable Computing Base (RCB). I introduce the concept of the RCB and discuss what constitutes the RCB of the ASTEROID system and other fault tolerance mechanisms. Thereafter I show three case studies that evaluate approaches to protecting RCB components and thereby aim to achieve a software stack that is fully protected against hardware errors

Digital imaging technology assessment: Digital document storage project

An ongoing technical assessment and requirements definition project is examining the potential role of digital imaging technology at NASA's STI facility. The focus is on the basic components of imaging technology in today's marketplace as well as the components anticipated in the near future. Presented is a requirement specification for a prototype project, an initial examination of current image processing at the STI facility, and an initial summary of image processing projects at other sites. Operational imaging systems incorporate scanners, optical storage, high resolution monitors, processing nodes, magnetic storage, jukeboxes, specialized boards, optical character recognition gear, pixel addressable printers, communications, and complex software processes

Working Notes from the 1992 AAAI Workshop on Automating Software Design. Theme: Domain Specific Software Design

The goal of this workshop is to identify different architectural approaches to building domain-specific software design systems and to explore issues unique to domain-specific (vs. general-purpose) software design. Some general issues that cut across the particular software design domain include: (1) knowledge representation, acquisition, and maintenance; (2) specialized software design techniques; and (3) user interaction and user interface