486 research outputs found

    Design and construction of a configurable full-field range imaging system for mobile robotic applications

    Get PDF
    Mobile robotic devices rely critically on extrospection sensors to determine the range to objects in the robot’s operating environment. This provides the robot with the ability both to navigate safely around obstacles and to map its environment and hence facilitate path planning and navigation. There is a requirement for a full-field range imaging system that can determine the range to any obstacle in a camera lens’ field of view accurately and in real-time. This paper details the development of a portable full-field ranging system whose bench-top version has demonstrated sub-millimetre precision. However, this precision required non-real-time acquisition rates and expensive hardware. By iterative replacement of components, a portable, modular and inexpensive version of this full-field ranger has been constructed, capable of real-time operation with some (user-defined) trade-off with precision

    An Efficient and Cost Effective FPGA Based Implementation of the Viola-Jones Face Detection Algorithm

    Get PDF
    We present an field programmable gate arrays (FPGA) based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping

    Towards a Scalable Hardware/Software Co-Design Platform for Real-time Pedestrian Tracking Based on a ZYNQ-7000 Device

    Get PDF
    Currently, most designers face a daunting task to research different design flows and learn the intricacies of specific software from various manufacturers in hardware/software co-design. An urgent need of creating a scalable hardware/software co-design platform has become a key strategic element for developing hardware/software integrated systems. In this paper, we propose a new design flow for building a scalable co-design platform on FPGA-based system-on-chip. We employ an integrated approach to implement a histogram oriented gradients (HOG) and a support vector machine (SVM) classification on a programmable device for pedestrian tracking. Not only was hardware resource analysis reported, but the precision and success rates of pedestrian tracking on nine open access image data sets are also analysed. Finally, our proposed design flow can be used for any real-time image processingrelated products on programmable ZYNQ-based embedded systems, which benefits from a reduced design time and provide a scalable solution for embedded image processing products

    Design and Implementation of an Embedded Vision System for Industrial Robots

    Get PDF
    Enhanced vision system attached to any industrial robot undoubtedly increases its accuracy and precision. Today, vision in industrial robots is facilitated almost exclusively via external or fixed cameras which may cause rather inconvenience due to obstacles in the line of sight. In this master thesis project, an Embedded Vision System is designed and developed to stream live video of a robot's focus point while being attached to its arm/actuator. Within the scope of this work, a working prototype has been achieved which is capable of producing live video stream on 640 X 480 resolution with a frame rate slightly above 9 FPS, having 256 colors for each pixel, displayable on a regular LCD display monitor. The system has been realized in a Spartan 6 platform and an Aptina image sensor has been used to acquire pixel information. I2C interfacing has been used to program the image sensor, data transfers have been facilitated by DMA cores, an off-chip DDR2 memory has been used for frame buffer and HDMI has been used as video out. Feasibility of adding Ethernet transmission capability has also been investigated

    SOC integration for video processing application

    Get PDF
    Video processing is an additional system that can improve the functionality of video surveillance. Integration of a simple video processing system into a complete camera system with a field-programmable gate array (FPGA) is an important step for research, to further improve the tracking process. This paper presents the integration of greyscale conversion into a complete camera system using Nios II software build tools for Eclipse. The camera system architecture is designed using the Nios II soft-core embedded processor from Altera. The proposed greyscale conversion system is designed using the C programming language in Eclipse. Parts of the architecture design in the camera system are important if greyscale conversion is to take place in the processing, such as synchronous dynamic random-access memory (SDRAM) and a video decoder driver. The image or video is captured using a Terasic TRDB-D5M camera and the data are converted to RGB format using the video decoder driver. The converted data are shown in binary format and the greyscale conversion system extracts and processes the data. The processed data are stored in the SDRAM before being sent to a VGA monitor. The camera system and greyscale conversion system were developed using the Altera DE2-70 development platform. The data from the video decoder driver and SDRAM were examined to confirm that the data conversion matched greyscale conversion formulae. The converted data in the SDRAM correctly displayed the greyscale image on a VGA monitor

    Real Time Pedestrian Detection Using an Infrared Camera with a FPGA

    Get PDF
    This project focuses on using Infrared technology in partnership with various filtering algorithms to implement a pedestrian detection system on a Field Programmable Gate Array (FPGA). Currently pedestrians are the most vulnerable users of the road. Every day there are millions of vehicles on the road and conditions such as inclement weather, poor lighting, traffic and other road hazards restrict the visibility of drivers which increases the risk to pedestrians. In addition, human error is known to be one of the leading causes of accidents. With the use of a pedestrian detection system which utilizes infrared technology, we are able to remove some of the hazards and provide an additional sense of awareness to the driver to reduce the occurrence of accidents and save lives

    Autonomous Pedestrian Detection in Transit Buses

    Get PDF
    This project created a proof of concept for an automated pedestrian detection and avoidance system designed for transit buses. The system detects objects up to 12 meters away, calculates the distance from the system using a solid-state LIDAR, and determines if that object is human by passive infrared. This triggers a visual and sound warning. A Xilinx Zynq-SoC utilizing programmable logic and an ARM-based processing system drive data fusion, and an external power unit makes it configurable for transit-buses

    FPGA-based Image Analysis System for Cotton Classing

    Get PDF
    The design and implementation of an FPGA (field-programmable gate array) based image analysis system was undertaken to replace an older system whose components have become obsolete. Video from an analog camera is digitized by a video decoder. The data from the video decoder is stored in memory and then processed using an FPGA. The results are then transmitted over a universal serial bus (USB) to a host personal computer for additional processing. The system also controls the timing of a flash to correctly capture the images; it measures color and reflectance and is used to classify the quality of raw cotton by determining the concentration of impurities (e.g. leaves or trash). The original system is first described and the need for upgrading presented. The goals of the new system are then specified and its implementation presented along with the design space tradeoffs that were considered. Finally, the results obtained from using the new system are presented to demonstrate its effectiveness

    FPGA IMPLEMENTATION OF ZIEGLER-NICHOLS CLOSED-LOOP METHOD FOR AUTOMATIC PID PARAMETERS TUNING

    Get PDF
    A control loop is necessary in order to control a plant or system in order to gain low error system, robust system, or system with fast response depend on the purpose. The most commonly known and used control loop is Proportional-Integral/Proportional-Integral-Derivative. In order to gain the desired output, its parameters, which have different effects, have to be set according to the design requirements. Several methods can be used to determine the parameter; one of them is Ziegler-Nichols closed-loop method. The purpose of this project is to carry out FPGA implementation of Ziegler-Nichols closed-loop method for automatic PID parameters tuning. The commonly used design hardware for digital projects is microcontroller. Microcontroller device resources is limited, we do not know how much device resources this project will take, and to add an additional resources is quite complicated as well, therefore we choose FPGA instead. This project is part of a bigger project which consists of three projects, which are handled by a student each. The most important parts for this project are estimator and controller modules which are located in the FPGA. This is because the estimator’s function is to do the steps of the Ziegler-Nichols closed loop method and the controller is necessary because the estimator cannot function if there is no controller. To build and test out the system, it is necessary to begin from the subsystems. If the subsystem’s tests are successful, then the probability for the overall system to be success is higher. Experimental results show that the subsystems have been successfully designed, but the overall system could not be applied because the target Spartan 3E FPGA does not have sufficient logic resources on. The first and second objectives was achieved but the third objective was not achieved because this project could not be applied on the target FPGA and therefore this project has not been used on the real tools.Keywords – Auto-tuning PID controller, Ziegler-Nichols, FPGA Implementatio
    • 

    corecore