The emergence of a new supercomputer architecture

"July 1990".Includes bibliographical references (p. 25-26).Alan N. Afuah, James M. Utterback

Seymour Cray, visionary pioneer of supercomputing, is dead at 71

Seymour R. Cray, a computer industry pioneer and the father of the supercomputer, died October 5, at a hospital near his home in Colorado Springs. He was 71 and had been in the hospital since an automobile wreck two weeks ago. Officials at Penrose Community Hospital said the cause was the severe head injuries Cray had received in the accident

Infrared Sensors for Autonomous Vehicles

The spurt in interest and development of Autonomous vehicles is a continuing boost to the growth of electronic devices in the automotive industry. The sensing, processing, activation, feedback and control functions done by the human brain have to be replaced with electronics. The task is proving to be exhilarating and daunting at the same time. The environment sensors – RADAR (RAdio Detection And Ranging), Camera and LIDAR (Light Detection And Ranging) are enjoying a lot attention with the need for increasingly greater range and resolution being demanded by the “eyes” and faster computation by the “brain”. Even though all three and more sensors (Ultrasonic / Stereo Camera / GPS / etc.) will be used together; this chapter will focus on challenges facing Camera and LIDAR. Anywhere from 2 – 8 cameras and 1 – 2 LIDAR are expected to be part of the sensor suite needed by Autonomous vehicles – which have to function equally well in day and night. Near infrared (800 – 1000nm) devices are currently emitters of choice in these sensors. Higher range, resolution and Field of view pose many challenges to overcome with new electronic device innovations before we realize the safety and other benefits of autonomous vehicles

Critical design issues for gallium arsenide VLSI circuits.

The aim of this research was to design and evaluate various Gallium Arsenide circuit elements such as logic gates, adders and multipliers suitable for high speed VLSI circuits. The issues addressed are the logic gate design and optimisation, evaluation of various buffering schemes and the impact of the algorithm on adder and multiplier performance for digital signal processing applications. This has led to the development of a design approach to produce high speed and low power dissipation Gallium Arsenide VLSI circuits. This is achieved by : Evaluating the well established Direct Coupled Logic (DCFL) gates and proposing an alternative gate, namely the Source Follower DCFL (SDCFL), to improve the noise margin and speed. Suggesting various buffering schemes to maintain high speed in areas where the fanout loading is high (eg. clock drivers). Comparing various adder types in terms of delay-power and delay-area products to arrive at a suitable architecture for Gallium Arsenide implementation and to determine the influence of the algorithm and layout approach on circuit performance. To investigate this further, a multiplier was also designed to assess the performance at higher levels of integration. Applying a new layout approach, called the 'ring notation*, to the adder and multiplier circuits in order to improve their delay-area product. Finally, the critical factors influencing the performance of the circuits are reviewed and a number of suggestions are given to maintain reliable operation at high speed

Paths to light trapping in thin film GaAs solar cells

It is now well established that light trapping is an essential element of thin film solar cell design. Numerous light trapping geometries have already been applied to thin film cells, especially to silicon-based devices. Less attention has been paid to light trapping in GaAs thin film cells, mainly because light trapping is considered less attractive due to the material's direct bandgap and the fact that GaAs suffers from strong surface recombination, which particularly affects etched nanostructures. Here, we study light trapping structures that are implemented in a high-bandgap material on the back of the GaAs active layer, thereby not perturbing the integrity of the GaAs active layer. We study photonic crystal and quasi-random nanostructures both by simulation and by experiment and find that the photonic crystal structures are superior because they exhibit fewer but stronger resonances that are better matched to the narrow wavelength range where GaAs benefits from light trapping. In fact, we show that a 1500 nm thick cell with photonic crystals achieves the same short circuit current as an unpatterned 4000 nm thick cell. These findings are significant because they afford a sizeable reduction in active layer thickness, and therefore a reduction in expensive epitaxial growth time and cost, yet without compromising performance

Center for Space Microelectronics Technology

The 1990 technical report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the center during 1990. The report lists 130 publications, 226 presentations, and 87 new technology reports and patents

Center for space microelectronics technology

The 1992 Technical Report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the center during the past year. The report lists 187 publications, 253 presentations, and 111 new technology reports and patents in the areas of solid-state devices, photonics, advanced computing, and custom microcircuits

Background paper

This background paper focuses on the Federal role in supporting a national high-performance computing initiative. High-performance ‘‘supercomputers’ * are fast becoming tools of international competition and they play an important role in such areas as scientific research, weather forecasting, and popular entertainment. They may prove to be the key to maintaining America’s preeminence in science and engineering. The automotive, aerospace, electronic, and pharmaceutical industries are becoming more reliant on the use of high-performance computers in the analysis, engineering, design, and manufacture of high-technology products

Architectural Approaches For Gallium Arsenide Exploitation In High-Speed Computer Design

Continued advances in the capability of Gallium Arsenide (GaAs)technology have finally drawn serious interest from computer system designers. The recent demonstration of very large scale integration (VLSI) laboratory designs incorporating very fast GaAs logic gates herald a significant role for GaAs technology in high-speed computer design:1 In this thesis we investigate design approaches to best exploit this promising technology in high-performance computer systems. We find significant differences between GaAs and Silicon technologies which are of relevance for computer design. The advantage that GaAs enjoys over Silicon in faster transistor switching speed is countered by a lower transistor count capability for GaAs integrated circuits. In addition, inter-chip signal propagation speeds in GaAs systems do not experience the same speedup exhibited by GaAs transistors; thus, GaAs designs are penalized more severely by inter-chip communication. The relatively low density of GaAs chips and the high cost of communication between them are significant obstacles to the full exploitation of the fast transistors of GaAs technology. A fast GaAs processor may be excessively underutilized unless special consideration is given to its information (instructions and data) requirements. Desirable GaAs system design approaches encourage low hardware resource requirements, and either minimize the processor’s need for off-chip information, maximize the rate of off-chip information transfer, or overlap off-chip information transfer with useful computation. We show the impact that these considerations have on the design of the instruction format, arithmetic unit, memory system, and compiler for a GaAs computer system. Through a simulation study utilizing a set of widely-used benchmark programs, we investigate several candidate instruction pipelines and candidate instruction formats in a GaAs environment. We demonstrate the clear performance advantage of an instruction pipeline based upon a pipelined memory system over a typical Silicon-like pipeline. We also show the performance advantage of packed instruction formats over typical Silicon instruction formats, and present a packed format which performs better than the experimental packed Stanford MIPS format