666 research outputs found
Non-classical computing: feasible versus infeasible
Physics sets certain limits on what is and is not computable. These limits are very far from having been reached by current technologies. Whilst proposals for hypercomputation are almost certainly infeasible, there are a number of non classical approaches that do hold considerable promise. There are a range of possible architectures that could be implemented on silicon that are distinctly different from the von Neumann model. Beyond this, quantum simulators, which are the quantum equivalent of analogue computers, may be constructable in the near future
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Hardware implementations of computer-generated holography: a review
Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations
Development of 3-D Medical Image Visualization System
This paper reports the development of a holographic video (holovideo) rendering system that uses standard 2-D medical imaging inputs and generates medical images of human body parts as holographic video with three-dimensional (3-D) realism. The system generates 3-D medical images by transforming a numerical description of a scene (such as in data from URI, CAT, PET, and X-ray databases) into a holographic fringe pattern and then displays the images on the image volume of a holovideo display system. The system uses specialized digital signal processors to scale up the computation and rendering speed of the holovideo computing system beyond what exists today. Holograms developed under this research have horizontal (holographic) resolution high enough for smooth binocular parallax and a (video) resolution in the vertical direction comparable to NTSC television. Thus, the holovideo rendering and display system provides medical personnel with the information essential for viewing internal organs of humans with accurate 3-D realism. It is envisioned that the commercializable system that will ultimately be developed in the course of this research program will be compact enough to be used as desktop equipment in a medical imaging platform and economical enough to be made available in adequate numbers to hospitals
A volumetric display for visual, tactile and audio presentation using acoustic trapping
Science-fiction movies such as Star Wars portray volumetric systems that not only provide visual but also tactile and audible 3D content. Displays, based on swept volume surfaces, holography, optophoretics, plasmonics, or lenticular lenslets, can create 3D visual content without the need for glasses or additional instrumentation. However, they are slow, have limited persistence of vision (POV) capabilities, and, most critically, rely on operating principles that cannot also produce tactile and auditive content.
Here, we present for the first time a Multimodal Acoustic Trap Display (MATD): a mid-air volumetric display that can simultaneously deliver visual, auditory, and tactile content, using acoustophoresis as the single operating principle. Our system acoustically traps a particle and illuminates it with red, green, and blue light to control its colour as it quickly scans through our display volume. Using time multiplexing with a secondary trap, amplitude modulation and phase minimization, the MATD delivers simultaneous auditive and tactile content. The system demonstrates particle speeds of up to 8.75m/s and 3.75m/s in the vertical and horizontal directions respectively, offering particle manipulation capabilities superior to other optical or acoustic approaches demonstrated to date. Beyond enabling simultaneous visual, tactile and auditive content, our approach and techniques offer opportunities for non-contact, high-speed manipulation of matter, with applications in computational fabrication and biomedicine
Parallel and Distributed Computing
The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing
Center for Space Microelectronics Technology 1988-1989 technical report
The 1988 to 1989 Technical Report of the JPL Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the center. Listed are 321 publications, 282 presentations, and 140 new technology reports and patents
Roadmap on structured light
Structured light refers to the generation and application of custom light fields. As the tools and technology to create and detect structured light have evolved, steadily the applications have begun to emerge. This roadmap touches on the key fields within structured light from the perspective of experts in those areas, providing insight into the current state and the challenges their respective fields face. Collectively the roadmap outlines the venerable nature of structured light research and the exciting prospects for the future that are yet to be realized
Simulation of an FPGA implementation of holographic video generation in real time
Ankara : The Department of Electrical and Electronics Engineering and the Institute of Engineering and Sciences of Bilkent University, 2010.Thesis (Master's) -- Bilkent University, 2010.Includes bibliographical references leaves 94-97.Holography is a promising method for three-dimensional vision. Different
research efforts are being spent to improve generation of holograms and image
reconstruction from holograms. A computer generated hologram can be a
precise method of generating a real like video in the future. RayleighSommerfeld
diffraction method and Fresnel-Kirchhoff diffraction formula are
two algorithms suitable for FPGA implementation of hologram calculation.
Simulator image reconstructions and optical image reconstructions with spatial
light modulator using the generated holograms are compared and it is seen that
they are quite similar. A field programmable gate array (FPGA) implementation
of real time holographic video generation based on Rayleigh-Sommerfeld
formulation is simulated. FPGA implementation is tested and verified by a
computer simulator. An FPGA board capable of capturing video input and
giving video output for spatial light modulator (SLM) is chosen as the
implementation platform for simulations. A small size hologram calculator can
be implemented on the FPGA board. A custom board for specific hologram
calculation algorithm can be designed to increase the performance. Pipelined
architecture and SDRAM memories can be used to increase the performance.Yılmaz, Timur EyĂŒpM.S
Implementation of arithmetic primitives using truly deep submicron technology (TDST)
The invention of the transistor in 1947 at Bell Laboratories revolutionised the electronics industry and created a powerful platform for emergence of new industries. The quest to increase the number of devices per chip over the last four decades has resulted in rapid transition from Small-Scale-Integration (SSI) and Large-Scale-lntegration (LSI), through to the Very-Large-Scale-Integration (VLSI) technologies, incorporating approximately 10 to 100 million devices per chip. The next phase in this evolution is the Ultra-Large-Scale-Integration (ULSI) aiming to realise new application domains currently not accessible to CMOS technology. Although technology is continuously evolving to produce smaller systems with minimised power dissipation, the IC industry is facing major challenges due to constraints on power density (W/cm2) and high dynamic (operating) and static (standby) power dissipation. Mobile multimedia communication and optical based technologies have rapidly become a significant area of research and development challenging a variety of technological fronts. The future emergence or 4G (4th Generation) wireless communications networks is further driving this development, requiring increasing levels of media rich content. The processing requirements for capture, conversion, compression, decompression, enhancement and display of higher quality multimedia, place heavy demands on current ULSI systems. This is also apparent for mobile applications and intelligent optical networks where silicon chip area and power dissipation become primary considerations. In addition to the requirements for very low power, compact size and real-time processing, the rapidly evolving nature of telecommunication networks means that flexible soft programmable systems capable of adaptation to support a number of different standards and/or roles become highly desirable. In order to fully realise the capabilities promised by the 4G and supporting intelligent networks, new enabling technologies arc needed to facilitate the next generation of personal communications devices. Most of the current solutions to meet these challenges are based on various implementations of conventional architectures. For decades, silicon has been the main platform of computing, however it is slow, bulky, runs too hot, and is too expensive. Thus, new approaches to architectures, driving multimedia and future telecommunications systems, are needed in order to extend the life cycle of silicon technology. The emergence of Truly Deep Submicron Technology (TDST) and related 3-D interconnection technologies have provided potential alternatives from conventional architectures to 3-D system solutions, through integration of IDST, Vertical Software Mapping and Intelligent Interconnect Technology (IIT). The concept of Soft-Chip Technology (SCT) entails integration of Softâą Processing Circuits with Soft-Configurable Circuits . This concept can effectively manipulate hardware primitives through vertical integration of control and data. Thus the notion of 3-D Soft-Chip emerges as a new design algorithm for content-rich multimedia, telecommunication and intelligent networking system applications. 3âąD architectures (design algorithms used suitable for 3-D soft-chip technology), are driven by three factors. The first is development of new device technology (TDST) that can support new architectures with complexities of 100M to 1000M devices. The second is development of advanced wafer bonding techniques such as Indium bump and the more futuristic optical interconnects for 3-D soft-chip mapping. The third is related to improving the performance of silicon CMOS systems as devices continue to scale down in dimensions. One of the fundamental building blocks of any computer system is the arithmetic component. Optimum performance of the system is determined by the efficiency of each individual component, as well as the network as a whole entity. Development of configurable arithmetic primitives is the fundamental focus in 3-D architecture design where functionality can be implemented through soft configurable hardware elements. Therefore the ability to improve the performance capability of a system is of crucial importance for a successful design. Important factors that predict the efficiency of such arithmetic components are: âą The propagation delay of the circuit, caused by the gate, diffusion and wire capacitances within !he circuit, minimised through transistor sizing. and âą Power dissipation, which is generally based on node transition activity. [2] Although optimum performance of 3-D soft-chip systems is primarily established by the choice of basic primitives such as adders and multipliers, the interconnecting network also has significant degree of influence on !he efficiency of the system. 3-D superposition of devices can decrease interconnect delays by up to 60% compared to a similar planar architecture. This research is based on development and implementation of configurable arithmetic primitives, suitable to the 3-D architecture, and has these foci: âą To develop a variety of arithmetic components such as adders and multipliers with particular emphasis on minimum area and compatible with 3-D soft-chip design paradigm. âą To explore implementation of configurable distributed primitives for arithmetic processing. This entails optimisation of basic primitives, and using them as part of array processing. In this research the detailed designs of configurable arithmetic primitives are implemented using TDST O.l3”m (130nm) technology, utilising CAD software such as Mentor Graphics and Cadence in Custom design mode, carrying through design, simulation and verification steps
Zooplankton visualization system: design and real-time lossless image compression
In this thesis, I present a design of a small, self-contained, underwater plankton imaging system. I base the imaging systemâs design on an embedded PC architecture based on PC/104-Plus standards to meet the compact size and low power requirements. I developed a simple graphical user interface to run on a real-time operating system to control the imaging system. I also address how a real-time image compression scheme implemented on an FPGA chip speeds up image transfer speeds of the imaging system. Since lossless compression of the image is required in order to retain all image details, I began with an established compression scheme like SPIHT, and latter proposed a new compression scheme that suits the imaging systemâs requirements. I provide an estimate of the total amount of resources required and propose suitable FPGA chips to implement the compression scheme. Finally, I present various parallel designs by which the FPGA chip can be integrated into the imaging system
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