S-band antenna phased array communications system

The development of an S-band antenna phased array for spacecraft to spacecraft communication is discussed. The system requirements, antenna array subsystem design, and hardware implementation are examined. It is stated that the phased array approach offers the greatest simplicity and lowest cost. The objectives of the development contract are defined as: (1) design of a medium gain active phased array S-band communications antenna, (2) development and test of a model of a seven element planar array of radiating elements mounted in the appropriate cavity matrix, and (3) development and test of a breadboard transmit/receive microelectronics module

Index to NASA Tech Briefs, 1975

This index contains abstracts and four indexes--subject, personal author, originating Center, and Tech Brief number--for 1975 Tech Briefs

Beam lead technology

Beam lead technology for microcircuit interconnections with applications to metallization, passivation, and bondin

SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

Study to develop process controls for line certification on hybrid microcircuits Final report, Nov. 1970 - Feb. 1971

Basic process steps for fabrication of thick or thin film microcircuits for NASA us

Study of bonding methods for flip chip and beam leaded devices

The results are presented of a comprehensive study and evaluation for the bonding of flip chip and beam leaded devices onto hybrid microcircuit substrates used in high reliability space applications. The program included the evaluation of aluminum flip chips, solder (silver/tin) bump chips, gold beam leaded devices, and aluminum beam leaded devices

Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck–AT, Transition and Small Delay Defect Faults

The ever increasing complexity and size of digital circuits complemented by Deep Sub Micron (DSM) technology trends today pose challenges to the efficient Design For Test (DFT) methodologies. Innovation is required not only in designing the digital circuits, but also in automatic test pattern generation (ATPG) to ensure that the pattern set screens all the targeted faults while still complying with the Automatic Test Equipment (ATE) memory constraints. DSM technology trends push the requirements of ATPG to not only include the conventional static defects but also to include test patterns for dynamic defects. The current industry practices consider test pattern generation for transition faults to screen dynamic defects. It has been observed that just screening for transition faults alone is not sufficient in light of the continuing DSM technology trends. Shrinking technology nodes have pushed DFT engineers to include Small Delay Defect (SDD) test patterns in the production flow. The current industry standard ATPG tools are evolving and SDD ATPG is not the most economical option in terms of both test generation CPU time and pattern volume. New techniques must be explored in order to ensure that a quality test pattern set can be generated which includes patterns for stuck-at, transition and SDD faults, all the while ensuring that the pattern volume remains economical. This thesis explores the use of a “Top-Off” ATPG methodology to generate an optimal test pattern set which can effectively screen the required fault models while containing the pattern volume within a reasonable limit