453 research outputs found

    Unlocking the Next Generation of Nano-Satellite Missions with 320 Mbps Ka-Band Downlink: On-Orbit Results

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    Relatively low downlink data rates have historically limited the scientific and commercial return from CubeSats and SmallSats. As the capability of payloads for these satellites continues to increase, high-speed downlink capability is required to realize the increasing potential from these systems. In this paper we present the on-orbit results of our high-speed Ka-band transmitter operating aboard the twin Corvus-BC3 and Corvus-BC4 6U CubeSats. The 1-U form factor Ka-band system enables the unprecedented data return from a multi-spectral imager in this class of spacecraft. We highlight the spacecraft design and operational challenges that have been overcome on these missions that will enable high-speed downlink on any CubeSat or SmallSat. While the pointing requirements for this Ka-band downlink are readily achievable by today’s small satellites, we discuss some of the hidden complexities on both the attitude determination and control system (ADCS) as well as on the ground segment. Currently in-place ground infrastructure, including a 2.8 m dish at a downlink station in Svalbard, Norway, has enabled rapid commissioning and on-demand downlink several times a day for these sun-synchronous spacecraft. This paper includes flight data from early commission to routine operation at high-data rates. We believe the lessons learned on these missions will be valuable for other CubeSat developers that plan on moving away from UHF, S-band, and X-band and into the realm of millimeter microwave frequencies (such as 27 GHz)

    Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems

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    Computers have changed our lives beyond our own imagination in the past several decades. The continued and progressive advancements in VLSI technology and numerous micro-architectural innovations have played a key role in the design of spectacular low-cost high performance computing systems that have become omnipresent in today\u27s technology driven world. Performance and dependability have become key concerns as these ubiquitous computing machines continue to drive our everyday life. Every application has unique demands, as they run in diverse operating environments. Dependable, aggressive and adaptive systems improve efficiency in terms of speed, reliability and energy consumption. Traditional computing systems run at a fixed clock frequency, which is determined by taking into account the worst-case timing paths, operating conditions, and process variations. Timing speculation based reliable overclocking advocates going beyond worst-case limits to achieve best performance while not avoiding, but detecting and correcting a modest number of timing errors. The success of this design methodology relies on the fact that timing critical paths are rarely exercised in a design, and typical execution happens much faster than the timing requirements dictated by worst-case design methodology. Better-than-worst-case design methodology is advocated by several recent research pursuits, which exploit dependability techniques to enhance computer system performance. In this dissertation, we address different aspects of timing speculation based adaptive reliable overclocking schemes, and evaluate their role in the design of low-cost, high performance, energy efficient and dependable systems. We visualize various control knobs in the design that can be favorably controlled to ensure different design targets. As part of this research, we extend the SPRIT3E, or Superscalar PeRformance Improvement Through Tolerating Timing Errors, framework, and characterize the extent of application dependent performance acceleration achievable in superscalar processors by scrutinizing the various parameters that impact the operation beyond worst-case limits. We study the limitations imposed by short-path constraints on our technique, and present ways to exploit them to maximize performance gains. We analyze the sensitivity of our technique\u27s adaptiveness by exploring the necessary hardware requirements for dynamic overclocking schemes. Experimental analysis based on SPEC2000 benchmarks running on a SimpleScalar Alpha processor simulator, augmented with error rate data obtained from hardware simulations of a superscalar processor, are presented. Even though reliable overclocking guarantees functional correctness, it leads to higher power consumption. As a consequence, reliable overclocking without considering on-chip temperatures will bring down the lifetime reliability of the chip. In this thesis, we analyze how reliable overclocking impacts the on-chip temperature of a microprocessor and evaluate the effects of overheating, due to such reliable dynamic frequency tuning mechanisms, on the lifetime reliability of these systems. We then evaluate the effect of performing thermal throttling, a technique that clamps the on-chip temperature below a predefined value, on system performance and reliability. Our study shows that a reliably overclocked system with dynamic thermal management achieves 25% performance improvement, while lasting for 14 years when being operated within 353K. Over the past five decades, technology scaling, as predicted by Moore\u27s law, has been the bedrock of semiconductor technology evolution. The continued downscaling of CMOS technology to deep sub-micron gate lengths has been the primary reason for its dominance in today\u27s omnipresent silicon microchips. Even as the transition to the next technology node is indispensable, the initial cost and time associated in doing so presents a non-level playing field for the competitors in the semiconductor business. As part of this thesis, we evaluate the capability of speculative reliable overclocking mechanisms to maximize performance at a given technology level. We evaluate its competitiveness when compared to technology scaling, in terms of performance, power consumption, energy and energy delay product. We present a comprehensive comparison for integer and floating point SPEC2000 benchmarks running on a simulated Alpha processor at three different technology nodes in normal and enhanced modes. Our results suggest that adopting reliable overclocking strategies will help skip a technology node altogether, or be competitive in the market, while porting to the next technology node. Reliability has become a serious concern as systems embrace nanometer technologies. In this dissertation, we propose a novel fault tolerant aggressive system that combines soft error protection and timing error tolerance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing its output to the replicated pipeline registers. The organization of redundancy in the proposed Conjoined Pipeline system supports overclocking, provides concurrent error detection and recovery capability for soft errors, intermittent faults and timing errors, and flags permanent silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Back annotated post-layout gate-level timing simulations, using 45nm technology, of a conjoined two-stage arithmetic pipeline and a conjoined five-stage DLX pipeline processor, with forwarding logic, show that our approach, even under a severe fault injection campaign, achieves near 100% fault coverage and an average performance improvement of about 20%, when dynamically overclocked

    Computational structures for application specific VLSI processors

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    VLSI design methodology

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    Doctor of Philosophy

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    dissertationCommunication surpasses computation as the power and performance bottleneck in forthcoming exascale processors. Scaling has made transistors cheap, but on-chip wires have grown more expensive, both in terms of latency as well as energy. Therefore, the need for low energy, high performance interconnects is highly pronounced, especially for long distance communication. In this work, we examine two aspects of the global signaling problem. The first part of the thesis focuses on a high bandwidth asynchronous signaling protocol for long distance communication. Asynchrony among intellectual property (IP) cores on a chip has become necessary in a System on Chip (SoC) environment. Traditional asynchronous handshaking protocol suffers from loss of throughput due to the added latency of sending the acknowledge signal back to the sender. We demonstrate a method that supports end-to-end communication across links with arbitrarily large latency, without limiting the bandwidth, so long as line variation can be reliably controlled. We also evaluate the energy and latency improvements as a result of the design choices made available by this protocol. The use of transmission lines as a physical interconnect medium shows promise for deep submicron technologies. In our evaluations, we notice a lower energy footprint, as well as vastly reduced wire latency for transmission line interconnects. We approach this problem from two sides. Using field solvers, we investigate the physical design choices to determine the optimal way to implement these lines for a given back-end-of-line (BEOL) stack. We also approach the problem from a system designer's viewpoint, looking at ways to optimize the lines for different performance targets. This work analyzes the advantages and pitfalls of implementing asynchronous channel protocols for communication over long distances. Finally, the innovations resulting from this work are applied to a network-on-chip design example and the resulting power-performance benefits are reported

    Acceleration of Gapped Alignment in BLASTP Using the Mercury System

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    Protein databases have grown exponentially over the last decade. This exponential growth has made extracting valuable information from these databases increasingly time consuming. This project presents a new method of accelerating a commonly used program for performing similarity searching on protein databases, BLASTP. This project describes the design and implementation of Mercury BLASTP, a customized hardware accelerated variant of BLASTP. This project focuses on the gapped alignment stage of Mercury BLASTP and provides design details and implementation results

    Light-to-light readout system of the CMS electromagnetic calorimeter

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    For the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) at CERN, an 80,000-crystal electromagnetic calorimeter will measure electron and photon energies with high precision over a dynamic range of roughly 16 bits. The readout electronics will be located directly behind the crystals, and must survive a total dose of up to 2×104 Gy along with 5×1013 n/cm 2. A readout chain consisting of a custom wide-range acquisition circuit, commercial ADC and custom optical link for each crystal is presently under construction. An overview of the design is presented, with emphasis on the large-scale fiber communication syste

    Synthèse de réseaux de distribution d'horloges en présence de variations du procédé de fabrication

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    Design of clock distributions networks in presence of process variations -- Importance des variations spatiales de la constante de temps du transistor MOS -- Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations -- Conception de réseaux de distribution d'horloges fiables et à faible consommation de puissance -- Design of low-power and reliable logic-based H-trees -- Sources des variations spatiales de la constante de temps du transistor MOS -- Spatial characterization of process variations via MOS transistor time constants in VLSI & WSI -- Techniques de minimisation du biais de synchronisation par calibration de délai -- Minimizing process-induced skew using delay tuning
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