Hardware/software codesign methodology for fuzzy controller implementation

This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system

Hardware/software codesign of configurable fuzzy control systems

Fuzzy inference techniques are an attractive and well-established approach for solving control problems. This is mainly due to their inherent ability to obtain robust, low-cost controllers from the intuitive (and usually ambiguous or incomplete) linguistic rules used by human operators when describing the control process. This paper focuses on the hardware/software codesign of configurable fuzzy control systems. Two prototype systems implemented on general-purpose development boards are presented. In both of them, hardware components are based on specific and configurable fuzzy inference architecture whereas software tasks are supported by a microcontroller. The first prototype uses an off-the-shelf microcontroller and a low-complexity Xilinx XC4005XL field programmable gate array (FPGA). The second one is implemented as a system on programmable chip (SoPC), integrating the microcontroller together with the fuzzy hardware architecture and its interface circuits into a Xilinx Spartan2E200 FPGA.Comisión Interministerial de Ciencia y Tecnología TIC2001-1726-C02-0

Intelligent Embedded Software: New Perspectives and Challenges

Intelligent embedded systems (IES) represent a novel and promising generation of embedded systems (ES). IES have the capacity of reasoning about their external environments and adapt their behavior accordingly. Such systems are situated in the intersection of two different branches that are the embedded computing and the intelligent computing. On the other hand, intelligent embedded software (IESo) is becoming a large part of the engineering cost of intelligent embedded systems. IESo can include some artificial intelligence (AI)-based systems such as expert systems, neural networks and other sophisticated artificial intelligence (AI) models to guarantee some important characteristics such as self-learning, self-optimizing and self-repairing. Despite the widespread of such systems, some design challenging issues are arising. Designing a resource-constrained software and at the same time intelligent is not a trivial task especially in a real-time context. To deal with this dilemma, embedded system researchers have profited from the progress in semiconductor technology to develop specific hardware to support well AI models and render the integration of AI with the embedded world a reality

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

Network-aware design-space exploration of a power-efficient embedded application

The paper presents the design and multi-parameter optimization of a networked embedded application for the health-care domain. Several hardware, software, and application parameters, such as clock frequency, sensor sampling rate, data packet rate, are tuned at design- and run-time according to application specifications and operating conditions to optimize hardware requirements, packet loss, power consumption. Experimental results show that further power efficiency can be achieved by considering also communication aspects during design space exploratio

Wearable flexible lightweight modular RFID tag with integrated energy harvester

A novel wearable radio frequency identification (RFID) tag with sensing, processing, and decision-taking capability is presented for operation in the 2.45-GHz RFID superhigh frequency (SHF) band. The tag is powered by an integrated light harvester, with a flexible battery serving as an energy buffer. The proposed active tag features excellent wearability, very high read range, enhanced functionality, flexible interfacing with diverse low-power sensors, and extended system autonomy through an innovative holistic microwave system design paradigm that takes antenna design into consideration from the very early stages. Specifically, a dedicated textile shorted circular patch antenna with monopolar radiation pattern is designed and optimized for highly efficient and stable operation within the frequency band of operation. In this process, the textile antenna's functionality is augmented by reusing its surface as an integration platform for light-energy-harvesting, sensing, processing, and transceiver hardware, without sacrificing antenna performance or the wearer's comfort. The RFID tag is validated by measuring its stand-alone and on-body characteristics in free-space conditions. Moreover, measurements in a real-world scenario demonstrate an indoor read range up to 23 m in nonline-of-sight indoor propagation conditions, enabling interrogation by a reader situated in another room. In addition, the RFID platform only consumes 168.3 mu W, when sensing and processing are performed every 60 s

Rationale for and design of a generic tiled hierarchical phased array beamforming architecture

The purpose of the phased array beamforming project is to develop a generic flexible efficient phased array receiver platform, using a mixed signal hardware/software-codesign approach. The results will be applicable to any radio (RF) system, but we will focus on satellite receiver (DVB-S) and radar applications. We will present a preliminary mapping of beamforming processing on a tiled architecture and determine its scalability.\ud \ud The functionality, size and cost constraints imply an integrated mixed signal CMOS solution. For a generic flexible multi-standard solution, a software defined radio approach is taken. Because a scalable and dependable solution is needed, a tiled hierarchical architecture is proposed with reconfigurable hardware to regain flexibility. A mapping is provided of beamforming on the proposed architecture. The advantages and disadvantages of each solution are discussed with respect to applicability and scalability.\ud \ud Different beamforming processing solutions can be mapped on the same proposed tiled hierarchical architecture. This provides a flexible, scalable and reconfigurable solution for a wide application domain. Beamforming is a data-driven streaming process which lends itself well for a regular scalable architecture. Beamsteering on the other hand is much more control-oriented and future work will focus on how to support beamsteering on the proposed architecture as well