Realizing live sequence charts in SystemVerilog.

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications

From MARTE to Reconfigurable NoCs: A model driven design methodology

Due to the continuous exponential rise in SoC's design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this paper, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis

A Model-Based Development and Verification Framework for Distributed System-on-Chip Architecture

The capabilities and thus, design complexity of VLSI-based embedded systems have increased tremendously in recent years, riding the wave of Moore’s law. The time-to-market requirements are also shrinking, imposing challenges to the designers, which in turn, seek to adopt new design methods to increase their productivity. As an answer to these new pressures, modern day systems have moved towards on-chip multiprocessing technologies. New architectures have emerged in on-chip multiprocessing in order to utilize the tremendous advances of fabrication technology. Platform-based design is a possible solution in addressing these challenges. The principle behind the approach is to separate the functionality of an application from the organization and communication architecture of hardware platform at several levels of abstraction. The existing design methodologies pertaining to platform-based design approach don’t provide full automation at every level of the design processes, and sometimes, the co-design of platform-based systems lead to sub-optimal systems. In addition, the design productivity gap in multiprocessor systems remain a key challenge due to existing design methodologies. This thesis addresses the aforementioned challenges and discusses the creation of a development framework for a platform-based system design, in the context of the SegBus platform - a distributed communication architecture. This research aims to provide automated procedures for platform design and application mapping. Structural verification support is also featured thus ensuring correct-by-design platforms. The solution is based on a model-based process. Both the platform and the application are modeled using the Unified Modeling Language. This thesis develops a Domain Specific Language to support platform modeling based on a corresponding UML profile. Object Constraint Language constraints are used to support structurally correct platform construction. An emulator is thus introduced to allow as much as possible accurate performance estimation of the solution, at high abstraction levels. VHDL code is automatically generated, in the form of “snippets” to be employed in the arbiter modules of the platform, as required by the application. The resulting framework is applied in building an actual design solution for an MP3 stereo audio decoder application.Siirretty Doriast

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

The increasing processing power of today’s HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).The work leading to these results has received funding from the European Community’s Seventh Framework Programme FP7/2007-2011 under grant agreement no. 611146

Modeling Networks-on-Chip at System Level with the MARTE UML profile

International audienceThe study of Networks on Chips (NoCs) is a research field that primarily addresses the global communication in Systems-on-Chip (SoCs). The selected topology and the routing algorithm play a prime role in the performance of NoC architectures. In order to handle the design complexity and meet the tight time-to-market constraints, it is important to automate most of these NoC design phases. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) specifies some concepts for model-based design and analysis of real time and embedded systems. This paper presents a MARTE based methodology for modeling concepts of NoC based architectures. It aims at improving the effectiveness of the MARTE standard by clarifying some notations and extending some definitions in the standard, in order to be able to model complex architectures like NoCs

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

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A model-driven method for the systematic literature review of qualitative empirical research

This paper explores a model-driven method for systematic literature reviews (SLRs), for use where the empirical studies found in the literature search are based on qualitative research. SLRs are an important component of the evidence-based practice (EBP) paradigm, which is receiving increasing attention in information systems (IS) but has not yet been widely-adopted. We illustrate the model-driven approach to SLRs via an example focused on the use of BPMN (Business Process Modelling Notation) in organizations. We discuss in detail the process followed in using the model-driven SLR method, and show how it is based on a hermeneutic cycle of reading and interpreting, in order to develop and refine a model which synthesizes the research findings of previous qualitative studies. This study can serve as an exemplar for other researchers wishing to carry out model-driven SLRs. We conclude with our reflections on the method and some suggestions for further researc

UML as a system level design methodology with application to software radio

Master'sMASTER OF SCIENC

A framework for developing engineering design ontologies within the aerospace industry

This paper presents a framework for developing engineering design ontologies within the aerospace industry. The aim of this approach is to strengthen the modularity and reuse of engineering design ontologies to support knowledge management initiatives within the aerospace industry. Successful development and effective utilisation of engineering ontologies strongly depends on the method/framework used to develop them. Ensuring modularity in ontology design is essential for engineering design activities due to the complexity of knowledge that is required to be brought together to support the product design decision-making process. The proposed approach adopts best practices from previous ontology development methods, but focuses on encouraging modular architectural ontology design. The framework is comprised of three phases namely: (1) Ontology design and development; (2) Ontology validation and (3) Implementation of ontology structure. A qualitative research methodology is employed which is composed of four phases. The first phase defines the capture of knowledge required for the framework development, followed by the ontology framework development, iterative refinement of engineering ontologies and ontology validation through case studies and experts’ opinion. The ontology-based framework is applied in the combustor and casing aerospace engineering domain. The modular ontologies developed as a result of applying the framework and are used in a case study to restructure and improve the accessibility of information on a product design information-sharing platform. Additionally, domain experts within the aerospace industry validated the strengths, benefits and limitations of the framework. Due to the modular nature of the developed ontologies, they were also employed to support other project initiatives within the case study company such as role-based computing (RBC), IT modernisation activity and knowledge management implementation across the sponsoring organisation. The major benefit of this approach is in the reduction of man-hours required for maintaining engineering design ontologies. Furthermore, this approach strengthens reuse of ontology knowledge and encourages modularity in the design and development of engineering ontologies

Model Based System Engineering for the development of System on Chip

Abstract. Model Based System Engineering (MBSE) has been utilized in auto manufacturing industries, airplane manufacturing and maintenance, and factory process automation industries. These are some of the complex fields. As SoC design is a complex process and requires years of work, MBSE can reduce time, complexity, reuse, and maintenance costs. It seems a fruitful idea/decision to take MBSE into use in SoC design depending on the previously mentioned elements. System on Chip (SoC) is obtaining the interest of many big companies. Therefore, MBSE will represent a huge competitive advantage once it is taken fully into the systems engineering roles of SoC. The existence of geographically dispersed teams, complexity of systems, interdisciplinarity, personalized system description, and their integration can be enabled by MBSE. As an emerging paradigm for the systems of the 21st century, MBSE paved the way for creating successful systems (for the companies) that are end to end connected. This research focuses on making use of MBSE in SoC. The thesis will show how SoC processes can be implemented in one complete model with top to bottom approach. Firstly, the traditional systems engineering approach has been explained with its tools and examples. Secondly, the need for taking up MBSE by the systems engineers is expressed. This contains the applications, use in modern systems, and benefits of MBSE. Moreover, MBSE methodology tools, languages, and their use in SoC is illustrated with examples. As SoC development is a huge and complex process; therefore, a small component of the chip has been taken in consideration for the purpose of understanding and making of the thesis. MBSE is a model-based approach hence a language needs to be present to produce these models and that language is SysML and OPD/OPL. SysML language and MagicDraw tool is used for expressing the architecture of the system. MagicDraw supports several external evaluators for evaluation of expressions and MATLAB is one of them. With MagicDraw we can do simulations, input parameters, and analyze data by processing on it using algorithms developed in MATLAB