Using proof failures to help debugging MAS

International audienceFor several years, we have worked on the usage of theorem proving techniques to validate Multi-Agent Systems. In this article, we present a preliminary case study, that is part of larger work whose long-term goal is to determine how proof tools can be used to help to develop error-free Multi-Agent Systems. This article describes how an error caused by a synchronisation problem between several agents can be identied by a proof failure. We also show that analysing proof failures can help to nd bugs that may occur only in a very particular context, which makes it dicult to analyse by standard debugging techniques. 1 Introduction This article takes place in the general context of the validation of Multi-Agents Systems, and more specically in the tuning stage. Indeed, for several years now, we have worked on the validation of MAS thanks to proof techniques. This is why the designed the GDT4MAS model (Mermet and Simon, 2009) has been designed, which provides both formal tools to speciy Multi-Agent Systems and a proof system that generates automatically , from a formal specication, a set of Proof Obligations that must be proven to guarantee the correctness of the system. In the same time, we have begun to study how to answer to the following question: What happens if the theorem prover does not manage to carry out the proof ?. More precisely, is it possible to learn anything from this failures (that we call in the sequel proof failures), in order to de-bug the MAS ? Answering to this question in a general context is tricky. Indeed, a rst remark is that a proof failure may occur in three dierent cases: • rst case: a true theorem is not provable (Gödel Incompleteness Theorem). Indeed, theorems generated by GDT4MAS are rst-order logic formulae, with arithmetic, which is typically the contexy where Gödel has established that there are non provable true theorems; • second case: a true theorem can not be automatically proven by the prover because rst-ordre logic is semidecidable. It means that there is not any automatic strategy that can prove all probable theorems. An ad hoc strategy must be provided by an expert. • third case: an error in the MAS specication has led to generate a false theorem that, hence, cannot be proven. So, when a proof failure is considered, the rst problem is to determine the case it corresponds to. It would be rather long and o-topic to give complete explanations here. However, it is important to knwow that the proof system has been designed to generate theorems that have good chances to be proven by standard strategies of provers, without requiring the expertise of a human. Moreover, unprovable true theorems generally do not correspond to real cases. Thus, in most cases, a proof failure will correspond to a mistake in the specication, and this is the context that is considered in the sequel. The subject of our study is then the following: if some generated proof obligations are note proven automatically, can we learn from that in order to help to correct the specication of the MAS ? So, the main idea is to check wether proof failures can be used to detect, even correct bugs in the specication of the MAS. Indeed, contrary to what is presented in (Das-tani and Meyer, 2010), where authors conside

Wireless System on Virtual Platform Evaluation

The most common way to develop System-on-Chip's (SoC) today is to utilize hardware design on a Field programmable gate array (FPGA). By utilizing the hardware on an FPGA, the opportunity to verify the hardware and start software design before implementing the final solution on silicon is possible. However, using an FPGA as a reference model for a final design gives a slightly imprecise estimation regarding required hardware such as memory and bus sizes. Trying to counteract this weakness, specific Electronic System-Level (ESL) Design tools has been developed in order to simplify production and increase capabilities to analyze and optimize during the developing phase. ARM SoC Designer is such a tool which provides a virtual environment for simulation of integrated SoC’s to simulate whole systems at a cycle accurate level. This Master's Thesis intend to evaluate ARM SoC Designer aspects and validity as an alternative to an FPGA when implementing and verifying a larger SoC system. To provide a thorough assessment of ARM SoC Designer, a cycle accurate model of the digital signal processing system of a general NB-IoT system was to be built and verified. Results shown, reveal that an implementation in ARM SoC Designer can be a valid representation of a preexisting wireless NB-IoT system currently developed on an FPGA board. Also that SoC Designer adds some very useful functionalities to traditional SoC development techniques but not without some significant flaws.With rising complexity and highly competitive market of integrated circuits, new techniques to develop embedded systems are always needed in order to secure the quality and to streamline the production of circuits. The tool ARM SoC Designer tries to accomplish this through adjusting traditional System-on-Chip development by adding debugging and troubleshooting capabilities not present in current design techniques. The question is, will the use of SoC Designer help? A System-on-Chip (SoC) is an especially designed chip that combines required electronic circuits of different components onto a single integrated chip, usually not bigger than a thumbnail. By directly building a chip containing all desired components instead of assemble multiple chips together makes it possible to manufacture the chips as small as possible and at the same time make them faster and more energy efficient than before. But the tininess of a SoC and the numerous amount components it is going to contain makes it also to a very complex system with a long and expensive developing process, where faults and errors are very hard to find and eliminate. The procedure of designing and developing SoC have been almost the same for a very long time. But with the rising demands on chips with more capacity in less area puts a lot of pressure on the manufacturers in the industry. Therefore manufacturers and developers have been starting to look for better design tools to increase the possibility to analyze and optimize during development. One of these tools are ARM SoC Designer which provides a virtual environment for simulation of integrated SoC's with the promise of great debugging and verifying capabilities. ARM SoC Designer are able to do this by allowing the user to simulate the process step by step and to easily modify system parameters. In order to evaluate ARM SoC Designer, a virtual model of an existing wireless system was built, tested and verified in the virtual environment. Different tests to analyze performance, accuracy, and debug- and troubleshooting capabilities were constructed and performed. With results showing great promise in categories accuracy and debugging, but left some things to be desired with performance and usability. This thesis can confirm that ARM SoC Designer does deliver an accurate representation of a SoC and that the verification capabilities are extremely helpful during implementation and testing. But, at the current performance in combination with a less good user experience, a steep learning curve and scarce documentation makes it difficult to recommend during a daily development basis. However, ARM SoC Designer shows a lot of promise if the usability can be enhanced slightly and performance be improved upon to such an extent that downtime of simulations won't be the majority of time consumed during usage

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Including context in a routing algorithm for the internet of things

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia InformáticaThe “Internet of Things” assumes that a large number of devices which are used on a daily basis will eventually become connected to the Internet. This scenario will provide room for a large set of new applications, however the network connections of an enormous set of nodes, which can be connected and disconnected, can move around and which have limitations with regards to their processing and communication capabilities, raises the need for the development of new message routing algorithms, different from those being in use today. In this thesis, a contribution is made towards the development of this type of algorithms. In particular, the idea which is tested is whether routing algorithms can improve their performance at various levels, such as, message delivery time, number of messages lost, power consumption, etc., if in the routing decisions these algorithms can make use of the concept of “Context”. Within the framework of this thesis, the “Context” is the organized collection of information which the routing algorithm collects from the environment surrounding the network nodes, and which allows it to make better routing decisions. This information can be related to low-level issues, such as, node location, power required to send a message, etc., as well as, with constraints related to the application, such as, message priority, maximum delivery time, etc. In order to evaluate this approach, this thesis proposes a routing algorithm called C-AODV. As the name suggests, it is based on the ADOV algorithm, however it is modified in several aspects; in particular, the possibility of using information collected from the context can be utilized to improve message routing. In order to test the proposed solution, several tests were performed on the NS-3 simulator which allowed the evaluation of the algorithm functionalities. The tests performed indicate that the proposed solution is valid

Modular event-driven unmanned aerial vehicles control platform

Hoje em dia, os drones estão-se a tornar cada vez mais comuns nas nossas vidas diárias. Com a agilidade, acessibilidade e diversidade dos drones, eles são uma excelente plataforma para transportar dispositivos (p.ex., conjunto de sensores, câmeras, unidades computacionais de pequena dimensão). Assim sendo, são uma excelente ferramenta para tarefas como: explorar e estudar áreas perigosas, monitorizar campos de agricultura, ajudar na detecção e combate de incêndios ou vigiar multidões. Para realizar tais tarefas, ferramentas de automação e integração são essenciais, para que o desenvolvimento se concentre na própria aplicação e não nos problemas relacionados com a integração e automação do sistema do drone. Os drones atualmente disponiveis não são capazes de lidar com tais complexidades de forma tão transparente. Por exemplo, certos niveis de automação são ja possiveis, mas requerem hardware e software especificos do fornecedor; no que toca a integração, alguns já supportam SDK ou API para interagir com o drone, mas mais uma vez com a inconveniência de necessitar de conhecimento prévio sobre os sistemas dos drones. Para responder a estas necessidades, esta tese propõe uma plataforma modular de controlo baseada em eventos para abstrair os processos de automação e integração da complexidade subjacentes aos drones. Enquanto que a plataforma permite que as aplicações controlem e interajam com os drones, a sua complexidade é resolvida dentro da plataforma, simplificando o processo de integração. Além disso, com a plataforma proposta, a automação e funcionalidades do drone podem ser estendidas para estender as funcionalidades de drones mais limitados. A plataforma desenvolvida foi testada em diferentes cenários, tanto ao nível das suas funcionalidades como ao nível da analise de desempenho. Os resultados mostram que, além das funcionalidades suportadas, a plataforma consegue suportar o controlo e gestão de pelo menos até 64 drones em simultâneo sem ter modificações significativas nos atrasos de comunicação e throughput.Nowadays, drones are becoming more common in our daily lives. Since drones are agile, a ordable and diverse, they make an excellent platform to carry devices around (e.g., sensor arrays, cameras, small computers). With these capabilities, they become an excellent tool for tasks like: explore and study hazardous areas, agriculture monitoring, help on the detection and ght in res, and crowd surveillance. To perform such tasks, automation and integration tools are a must have, so that the development can focus on the application itself and not on the issues related with the integration and automation of the drone system. Current available drones are not capable of properly handling such complexities in a seamless way. For instance, some levels of automation are already possible, but require vendor speci c hardware and software; for integration, some o er SDK or API interactions, but once again with the inconvenience of requiring extensive knowledge about drone systems to implement. To address these issues, this thesis proposes a modular event-driven control platform to abstract automation and integration processes from the underlying complexities of the drones, while the platform lets the applications control and interact with the drones. The drones' complexities are resolved within the platform, therefore simplifying integration process. Moreover, with the proposed platform, drone automation and functionality can be extended across distinct brands of drones, while some may already support some features, others may not, and in that case the platform modules may intervene to extend the features of less capable drones. The developed platform has been tested in di erent scenarios, such as in terms of its functionalities and in terms of performance analysis. The results show that, besides the supported functionalities, the platform is able to handle the control and management of at last 64 simultaneous drones without signi cant changes in the communication delays and throughput.Mestrado em Engenharia Informátic

Automotive Stirling engine development program

This is the ninth Semiannual Technical Progress Report prepared under the Automotive Stirling Engine Development Program. It covers the twenty-eighth and twenty-ninth quarters of activity after award of the contract. Quarterly Technical Progress Reports related program activities from the first through the thirteenth quarters; thereafter, reporting was changed to a Semiannual format. This report summarizes the study of higher-power kinematic Stirling engines for transportation use, development testing of Mod I Stirling engines, and component development activities. Component development testing included successful conical fuel nozzle testing and functional checkout of Mod II controls and auxiliaries on Mod I engine test beds. Overall program philosophy is outlined and data and test results are presented