4,031 research outputs found
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
In modern VLSI design flow, the register-transfer level (RTL) stage is a
critical point, where designers define precise design behavior with hardware
description languages (HDLs) like Verilog. Since the RTL design is in the
format of HDL code, the standard way to evaluate its quality requires
time-consuming subsequent synthesis steps with EDA tools. This time-consuming
process significantly impedes design optimization at the early RTL stage.
Despite the emergence of some recent ML-based solutions, they fail to maintain
high accuracy for any given RTL design. In this work, we propose an innovative
pre-synthesis PPA estimation framework named MasterRTL. It first converts the
HDL code to a new bit-level design representation named the simple operator
graph (SOG). By only adopting single-bit simple operators, this SOG proves to
be a general representation that unifies different design types and styles. The
SOG is also more similar to the target gate-level netlist, reducing the gap
between RTL representation and netlist. In addition to the new SOG
representation, MasterRTL proposes new ML methods for the RTL-stage modeling of
timing, power, and area separately. Compared with state-of-the-art solutions,
the experiment on a comprehensive dataset with 90 different designs shows
accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative
slack (TNS), worst negative slack (WNS), and power, respectively.Comment: To be published in the Proceedings of 42nd IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), 202
GraPhSyM: Graph Physical Synthesis Model
In this work, we introduce GraPhSyM, a Graph Attention Network (GATv2) model
for fast and accurate estimation of post-physical synthesis circuit delay and
area metrics from pre-physical synthesis circuit netlists. Once trained,
GraPhSyM provides accurate visibility of final design metrics to early EDA
stages, such as logic synthesis, without running the slow physical synthesis
flow, enabling global co-optimization across stages. Additionally, the swift
and precise feedback provided by GraPhSym is instrumental for
machine-learning-based EDA optimization frameworks. Given a gate-level netlist
of a circuit represented as a graph, GraPhSyM utilizes graph structure,
connectivity, and electrical property features to predict the impact of
physical synthesis transformations such as buffer insertion and gate sizing.
When trained on a dataset of 6000 prefix adder designs synthesized at an
aggressive delay target, GraPhSyM can accurately predict the post-synthesis
delay (98.3%) and area (96.1%) metrics of unseen adders with a fast 0.22s
inference time. Furthermore, we illustrate the compositionality of GraPhSyM by
employing the model trained on a fixed delay target to accurately anticipate
post-synthesis metrics at a variety of unseen delay targets. Lastly, we report
promising generalization capabilities of the GraPhSyM model when it is
evaluated on circuits different from the adders it was exclusively trained on.
The results show the potential for GraPhSyM to serve as a powerful tool for
advanced optimization techniques and as an oracle for EDA machine learning
frameworks.Comment: Accepted at ICCAD'2
AI/ML Algorithms and Applications in VLSI Design and Technology
An evident challenge ahead for the integrated circuit (IC) industry in the
nanometer regime is the investigation and development of methods that can
reduce the design complexity ensuing from growing process variations and
curtail the turnaround time of chip manufacturing. Conventional methodologies
employed for such tasks are largely manual; thus, time-consuming and
resource-intensive. In contrast, the unique learning strategies of artificial
intelligence (AI) provide numerous exciting automated approaches for handling
complex and data-intensive tasks in very-large-scale integration (VLSI) design
and testing. Employing AI and machine learning (ML) algorithms in VLSI design
and manufacturing reduces the time and effort for understanding and processing
the data within and across different abstraction levels via automated learning
algorithms. It, in turn, improves the IC yield and reduces the manufacturing
turnaround time. This paper thoroughly reviews the AI/ML automated approaches
introduced in the past towards VLSI design and manufacturing. Moreover, we
discuss the scope of AI/ML applications in the future at various abstraction
levels to revolutionize the field of VLSI design, aiming for high-speed, highly
intelligent, and efficient implementations
Network Lasso: Clustering and Optimization in Large Graphs
Convex optimization is an essential tool for modern data analysis, as it
provides a framework to formulate and solve many problems in machine learning
and data mining. However, general convex optimization solvers do not scale
well, and scalable solvers are often specialized to only work on a narrow class
of problems. Therefore, there is a need for simple, scalable algorithms that
can solve many common optimization problems. In this paper, we introduce the
\emph{network lasso}, a generalization of the group lasso to a network setting
that allows for simultaneous clustering and optimization on graphs. We develop
an algorithm based on the Alternating Direction Method of Multipliers (ADMM) to
solve this problem in a distributed and scalable manner, which allows for
guaranteed global convergence even on large graphs. We also examine a
non-convex extension of this approach. We then demonstrate that many types of
problems can be expressed in our framework. We focus on three in particular -
binary classification, predicting housing prices, and event detection in time
series data - comparing the network lasso to baseline approaches and showing
that it is both a fast and accurate method of solving large optimization
problems
LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing
LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft
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