Using Disjoint Reachability for Parallelization

Abstract. We present a disjoint reachability analysis for Java. Our analysis com-putes extended points-to graphs annotated with reachability states. Each heap node is annotated with a set of reachability states that abstract the reachability of objects represented by the node. The analysis also includes a global pruning step which analyzes a reachability graph to prune imprecise reachability states that cannot be removed with local reasoning alone. We have implemented the analysis and used it to parallelize 9 benchmarks. Our evaluation shows the anal-ysis results are sufficiently precise to parallelize our benchmarks and achieve an average speedup of 16.9×.

SAT-Based Synthesis Methods for Safety Specs

Automatic synthesis of hardware components from declarative specifications is an ambitious endeavor in computer aided design. Existing synthesis algorithms are often implemented with Binary Decision Diagrams (BDDs), inheriting their scalability limitations. Instead of BDDs, we propose several new methods to synthesize finite-state systems from safety specifications using decision procedures for the satisfiability of quantified and unquantified Boolean formulas (SAT-, QBF- and EPR-solvers). The presented approaches are based on computational learning, templates, or reduction to first-order logic. We also present an efficient parallelization, and optimizations to utilize reachability information and incremental solving. Finally, we compare all methods in an extensive case study. Our new methods outperform BDDs and other existing work on some classes of benchmarks, and our parallelization achieves a super-linear speedup. This is an extended version of [5], featuring an additional appendix.Comment: Extended version of a paper at VMCAI'1

Structural Analysis: Shape Information via Points-To Computation

This paper introduces a new hybrid memory analysis, Structural Analysis, which combines an expressive shape analysis style abstract domain with efficient and simple points-to style transfer functions. Using data from empirical studies on the runtime heap structures and the programmatic idioms used in modern object-oriented languages we construct a heap analysis with the following characteristics: (1) it can express a rich set of structural, shape, and sharing properties which are not provided by a classic points-to analysis and that are useful for optimization and error detection applications (2) it uses efficient, weakly-updating, set-based transfer functions which enable the analysis to be more robust and scalable than a shape analysis and (3) it can be used as the basis for a scalable interprocedural analysis that produces precise results in practice. The analysis has been implemented for .Net bytecode and using this implementation we evaluate both the runtime cost and the precision of the results on a number of well known benchmarks and real world programs. Our experimental evaluations show that the domain defined in this paper is capable of precisely expressing the majority of the connectivity, shape, and sharing properties that occur in practice and, despite the use of weak updates, the static analysis is able to precisely approximate the ideal results. The analysis is capable of analyzing large real-world programs (over 30K bytecodes) in less than 65 seconds and using less than 130MB of memory. In summary this work presents a new type of memory analysis that advances the state of the art with respect to expressive power, precision, and scalability and represents a new area of study on the relationships between and combination of concepts from shape and points-to analyses

ParaPlan: A Tool for Parallel Reachability Analysis of Planar Polygonal Differential Inclusion Systems

Andrei Sandler, and Olga Tveretina, ‘ParaPlan: A Tool for Parallel Reachability Analysis of Planar Polygonal Differential Inclusion Systems’, in Patricia Bouyer, Andrea Orlandini and Pierluigi San Pietro, eds. Proceedings Eight International Symposium on Games, Automata, Logics and Formal Verification (GandALF 2017), Rome, Italy, 20-22 September 2017, Electronic Proceedings in Theoretical Computer Science, Vol. 256: 283-296, September 2017. © 2017 The Author(s). This work is licensed under the Creative Commons Attribution License CC BY 4.0 https://creativecommons.org/licenses/by/4.0/We present the ParaPlan tool which provides the reachability analysis of planar hybrid systems defined by differential inclusions (SPDI). It uses the parallelized and optimized version of the algorithm underlying the SPeeDI tool. The performance comparison demonstrates the speed-up of up to 83 times with respect to the sequential implementation on various benchmarks. Some of the benchmarks we used are randomly generated with the novel approach based on the partitioning of the plane with Voronoi diagrams

Efficient Set Sharing Using ZBDDs

Set sharing is an abstract domain in which each concrete object is represented by the set of local variables from which it might be reachable. It is a useful abstraction to detect parallelism opportunities, since it contains definite information about which variables do not share in memory, i.e., about when the memory regions reachable from those variables are disjoint. Set sharing is a more precise alternative to pair sharing, in which each domain element is a set of all pairs of local variables from which a common object may be reachable. However, the exponential complexity of some set sharing operations has limited its wider application. This work introduces an efficient implementation of the set sharing domain using Zero-suppressed Binary Decision Diagrams (ZBDDs). Because ZBDDs were designed to represent sets of combinations (i.e., sets of sets), they naturally represent elements of the set sharing domain. We show how to synthesize the operations needed in the set sharing transfer functions from basic ZBDD operations. For some of the operations, we devise custom ZBDD algorithms that perform better in practice. We also compare our implementation of the abstract domain with an efficient, compact, bit set-based alternative, and show that the ZBDD version scales better in terms of both memory usage and running time

Parallel Recursive State Compression for Free

This paper focuses on reducing memory usage in enumerative model checking, while maintaining the multi-core scalability obtained in earlier work. We present a tree-based multi-core compression method, which works by leveraging sharing among sub-vectors of state vectors. An algorithmic analysis of both worst-case and optimal compression ratios shows the potential to compress even large states to a small constant on average (8 bytes). Our experiments demonstrate that this holds up in practice: the median compression ratio of 279 measured experiments is within 17% of the optimum for tree compression, and five times better than the median compression ratio of SPIN's COLLAPSE compression. Our algorithms are implemented in the LTSmin tool, and our experiments show that for model checking, multi-core tree compression pays its own way: it comes virtually without overhead compared to the fastest hash table-based methods.Comment: 19 page

Towards parallelization of simulation-based reachability

To check bounded time invariant properties of models with nonlinear dynamics, one promising method is called simulation-based verification. This involves: (a) generating numerical simulations of the ODE from a finite set of representative initial states that cover the whole (uncountably many) initial set, say, (b) bloating each of these simulations by some factor such that the bloated tubes together over-approximate the reachable states from, and (c) checking if this computed over-approximation is adequate for proving invariance; otherwise, add more representative initial states to obtain a more precise over-approximation and repeat from (a). Compare-Execute-Check-Engine (C2E2) is such a tool for verifying bounded time dynamical and hybrid systems models using simulation-based reachability analysis. To make the reachable set computation more accurate, it is preferable to start from smaller initial sets, which requires C2E2 to partition large initial sets into smaller covers at first. However, the number of initial covers will increase exponentially with dimensionality of the system and the fidelity of each cover. Currently, C2E2 does invariant checking for the reachable sets from each cover sequentially, which makes the running time increase proportionally to the initial covers. Simulation-based approaches are naturally parallelizable due to the fact that simulations and reachable set computation for each initial condition considered can be computed independently. In this paper, we introduce the parallelization of C2E2 to utilize the computational power of multi-core CPU and improve the efficiency of tools. The parallel algorithm is implemented using thread library OPENMP. We evaluate the improvement of performance on four different models. Comparison with the sequential counterpart shows a maximum speedup of 7.3x on a four core Intel CPU I7-4790K processor.Ope