Automatic Generation of Geometrically Parameterized Reduced Order Models for Integrated Spiral RF-Inductors

In this paper we describe an approach to generating low-order models of spiral inductors that accurately capture the dependence on both frequency and geometry (width and spacing) parameters. The approach is based on adapting a multiparameter Krylov-subspace based moment matching method to reducing an integral equation for the three dimensional electromagnetic behavior of the spiral inductor. The approach is demonstrated on a typical on-chip rectangular inductor.Singapore-MIT Alliance (SMA

The Partial Elements Equivalent Circuit Method: The State Of The Art

This year marks about half a century since the birth of the technique known as the partial element equivalent circuit modeling approach. This method was initially conceived to model the behavior of interconnect-type problems for computer-integrated circuits. An important industrial requirement was the computation of general inductances in integrated circuits and packages. Since then, the advances in methods and applications made it suitable for modeling a large class of electromagnetic problems, especially in the electromagnetic compatibility (EMC)/signal and power integrity (SI/PI) areas. The purpose of this article is to present an overview of all aspects of the method, from its beginning to the present day, with special attention to the developments that have made it suitable for EMC/SI/PI problems

The analysis and modeling of fine pitch laminate interconnect in response to large energy fault transients

In embedded applications, the miniaturization of circuitry and functionality provides many benefits to both the producer and consumer. However, the benefits gained from miniaturization is not without penalty, as the environmental influences may be great enough to introduce system failures in new or different modes and effects;Of particular interest within this research is the effect of fault transients in reduced geometries of printed circuit card interconnect, commonly referred to as fine pitch laminate interconnect. Whereas larger geometries of conductor trace width and spacing may have been immune to circuit failure at a given fault input, the reduction of the trace geometry may introduce failures as the insulating effect of the dielectric is compromised to the point where arcing occurs;To address this concern, a circuit card was designed with fine pitch laminate features in microstrip, embedded microstrip, and stripline constructions. Various trace widths and separations were tested for structural integrity (presence of arcing or fusing) at voltage extremes defined in avionics standard. The specific trace widths in the test were 4 mils, 6 mils, 8 mils, and 12 mils, with the trace separation in each case equal to the trace widths. The results of the tests and methods to artificially improve the integrity of the interconnect are documented, providing a clear region of reliable operation to the designers and the engineering community;Finally, the construction of the interconnect and the results from the test were combined to create an empirical model for circuit analysis. Created for the Saber simulator, but readily adaptable to Spice, this model will describe high-speed operation of a propagating signal before breakdown, and uses data from the experiment to calculate threshold values for the arcing breakdown. The values for the breakdown voltages are correlated to the experimental data using statistical methods of weighted linear regression and hypothesis testing

Bubble memory module

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles