Calibration of DAC mismatch errors in sigma delta ADCs based on a sine-wave measurement

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit Sigma Delta-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration

The Nyquist criterion: a useful tool for the robust design of continuous-time ΣΔ modulators

This paper introduces a figure of merit for the robustness of continuous-time sigma-delta modulators. It is based on the Nyquist criterion for the equivalent discrete-time (DT) loop filter. It is shown how continuous-time modulators can be designed by optimizing this figure of merit. This way modulators with increased robustness against variations in the noise-transfer function (NTF) parameters are obtained. This is particularly useful for constrained systems, where the system order exceeds the number of design parameters. This situation occurs for example due to the effect of excess loop delay (ELD) or finite gain bandwidth (GBW) of the opamps. Additionally, it is shown that the optimization is equivalent to the minimization of H_infinity, the maximum out-of-band gain of the NTF. This explains why conventional design strategies that are based on H_infinity, such as Schreier’s approach, provide quite robust modulator designs in the case of unconstrained architectures

Multi-bit sigma-delta modulators with enhanced dynamic-range using non-linear DAC for hearing aids

15th IEEE International Conference on Electronics, Circuits and Systems, MaltaThis paper presents the possibility of employing nonlinear low-resolution DACs in the feedback paths of multi-bit second-order Sigma-Delta modulators. The proposed technique is particularly attractive in applications such as hearing aids, requiring a very large dynamic range and medium signal-tonoise-plus-distortion-ratio. As demonstrated through simulated results in which noise and mismatch effects are included, for the same over-sampling ratio, improvements in the order of 6-to-9 dB in the dynamic range can be achieved when comparing with the same topology employing linear-DACs

Cascaded feedforward sigma-delta modulator for wide bandwidth applications

[[abstract]]A new sigma-delta modulator architecture for wide bandwidth application called cascaded feedforward sigma-delta modulator is proposed in this paper. This sigma-delta modulator is similar to the conventional feedforward summation sigma-delta modulator. The conventional feedforward summation sigma-delta modulator uses multi-bit feedback and therefore a multi-bit digital-to-analog converter (DAC) is needed. Due to the nonlinearity of the multi-bit DAC, it is difficult to be implemented. On the other hand the proposed approach uses 1.5-bit feedback, and thus the implementation of the analog part is much easier than the conventional one. Since the 1.5-bit feedback will cause coarse quantization errors, error cancellation must be done in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the signal to noise plus distortion ratio (SNDR) of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide bandwidth application.[[notice]]補正完

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

Novel loop architectures for enhancing linearity and resolution of analog-to-digital converters

This paper proposes three mixed (analog and digital) loop architectures which involve an analog-to-digital converter and enhance its linearity and its resolution. Their benefits are discussed with mathematical models and high-level simulations (the ADC inserted in the loops is then a passive sigma-delta structure). One of the loop topologies is particularly highlighted: it is ideally able to enhance resolution by 5 bits without damaging bandwidth. The only added analog element is an active differential low-pass filter. The other operators are fully digital: a predictor and some models of the analog parts. The effect of some defaults, such as mismatch and common mode, is illustrated by high-level simulations. The needed accuracy for the digital parameters is evaluated to 16 bits. The test of a prototype realized in a 0.358m CMOS technology validates the principle and demonstrates that the critical element of the structure is the active differential filter

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

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