A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance

This paper presents an efficient and novel method for sequential learning of implications, invalid states, and tied gates. It can handle real industrial circuits, with multiple clock domains and partial set/reset. The application of this method to improve the efficiency of sequential ATPG is also demonstrated by achieving higher fault coverages and lower test generation times

Fault simulation and test generation for small delay faults

Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they model only a subset of delay defect behaviors. To solve this problem, a more realistic delay fault model has been developed which models delay faults caused by the combination of spot defects and parametric process variation. According to the new model, a realistic delay fault coverage metric has been developed. Traditional path delay fault coverage metrics result in unrealistically low fault coverage, and the real test quality is not reflected. The new metric uses a statistical approach and the simulation based fault coverage is consistent with silicon data. Fast simulation algorithms are also included in this dissertation. The new metric suggests that testing the K longest paths per gate (KLPG) has high detection probability for small delay faults under process variation. In this dissertation, a novel automatic test pattern generation (ATPG) methodology to find the K longest testable paths through each gate for both combinational and sequential circuits is presented. Many techniques are used to reduce search space and CPU time significantly. Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288. The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches

Improving rewiring scheme and its applications on various circuit design problems.

Lo Wing Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract --- p.iChapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Backgrounds and Definitions --- p.5Chapter 2.1.1 --- Boolean Network --- p.5Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6Chapter 2.1.5 --- Mandatory Assignments --- p.8Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Overview of FIRE --- p.15Chapter 3.3 --- Alternative Wire Identification Method --- p.17Chapter 3.3.1 --- Identifying Candidate Wires --- p.17Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21Chapter 3.5 --- Experimental Results --- p.26Chapter 3.6 --- Conclusions --- p.28Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33Chapter 4.4 --- Experimental Results --- p.37Chapter 4.5 --- Conclusions --- p.43Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45Chapter 5.1 --- Introduction --- p.45Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47Chapter 5.2.1 --- Problem Formulation --- p.47Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51Chapter 5.4 --- Experimental Results --- p.54Chapter 5.5 --- Conclusions --- p.57Chapter 6 --- Conclusions and Future Works --- p.58Bibliography --- p.6

At-Speed Path Delay Test

This research describes an approach to test metastability of flip-flops with help of multiple at-speed capture cycles during delay test. K longest paths per flip-flop test patterns are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. Traditional structural delay tests do not test whether time borrowing or stealing is working correctly, since only a single at-speed cycle is tested. To detect path delay faults for the multi-cycle paths, it is necessary to start a path at a register and end at a register while passing through another register, testing the longest paths between each pair of registers. This requires three or more at-speed cycles, rather than the two of traditional Launch on Capture test. This produces power supply noise closer to functional mode, and permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any other structural test technique. The path generation algorithm uses the circuit structure, and then the paths are sequentially justified using Boolean Satisfiability algorithms. The algorithm has been implemented in C++ on an Intel Core i7 machine. Experiments have been performed on various ISCAS benchmark circuits in both robust and non-robust path generation technique to evaluate our approach

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

High Quality Compact Delay Test Generation

Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra

Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths Per Gate (KLPG) test approach, which has additional necessary assignments on the paths. At the same time, some percentage of the flip-flops in the circuit will not scan, increasing the difficulty in test generation. In particular, there is no direct control on the outputs of those non-scan cells. All the non-scan cells that cannot be initialized are considered “uncontrollable” in the test generation process. They behave like “black boxes” and, thus, may block a potential path propagation, resulting in path delay test coverage loss. It is common for the timing critical paths in a circuit to pass through nodes influenced by the non-scan cells. In our work, we have extended the traditional Boolean algebra by including the “uncontrolled” state as a legal logic state, so that we can improve path coverage. Many path pruning decisions can be taken much earlier and many of the lost paths due to uncontrollable non-scan cells can be recovered, increasing path coverage and potentially reducing average CPU time per path. We have extended the existing traditional algebra to an 11-value algebra: Zero (stable), One (stable), Unknown, Uncontrollable, Rise, Fall, Zero/Uncontrollable, One/Uncontrollable, Unknown/Uncontrollable, Rise/Uncontrollable, and Fall/Uncontrollable. The logic descriptions for the NOT, AND, NAND, OR, NOR, XOR, XNOR, PI, Buff, Mux, TSL, TSH, TSLI, TSHI, TIE1 and TIE0 cells in the ISCAS89 benchmark circuits have been extended to the 11-value truth table. With 10% non-scan flip-flops, improved path delay fault coverage has been observed in comparison to that with the traditional algebra. The greater the number of long paths we want to test; the greater the path recovery advantage we achieve using our algebra. Along with improved path recovery, we have been able to test a greater number of transition fault sites. In most cases, the average CPU time per path is also lower while using the 11-value algebra. The number of tested paths increased by an average of 1.9x for robust tests, and 2.2x for non-robust tests, for K=5 (five longest rising and five longest falling transition paths through each line in the circuit), using the eleven-value algebra in contrast to the traditional algebra. The transition fault coverage increased by an average of 70%. The improvement increased with higher K values. The CPU time using the extended algebra increased by an average of 20%. So the CPU time per path decreased by an average of 40%. In future work, the extended algebra can achieve better test coverage for memory intensive circuits, circuits with logic black boxes, third party IPs, and analog units

Observability Driven Path Generation for Delay Test

This research describes an approach for path generation using an observability metric for delay test. K Longest Path Per Gate (KLPG) tests are generated for sequential circuits. A transition launched from a scan flip-flop (SFF) is captured into another SFF during at-speed clock cycles, that is, clock cycles at the rated design speed. The generated path is a ‘longest path’ suitable for delay test. The path generation algorithm then utilizes observability of the fan-out gates in the consecutive, lower-speed clock cycles, known as coda cycles, to generate paths ending at a SFF, to capture the transition from the at-speed cycles. For a given clocking scheme defined by the number of coda cycles, if the final flip-flop is not scan-enabled, the path generation algorithm attempts to generate a different path that ends at a SFF, located in a different branch of the circuit fan-out, indicated by lower observability. The paths generated over multiple cycles are sequentially justified using Boolean satisfiability. The observability metric optimizes the path generation in the coda cycles by always attempting to grow the path through the branch with the best observability and never generating a path that ends at a non-scan flip-flop. The algorithm has been developed in C++. The experiments have been performed on an Intel Core i7 machine with 64GB RAM. Various ISCAS benchmark circuits have been used with various KLPG configurations for code evaluation. Multiple configurations have been used for the experiments. The combinations of the values of K [1, 2, 3, 4, 5] and number of coda cycles [1, 2, 3] have been used to characterize the implementation. A sublinear rise is run time has been observed with increasing K values. The total number of tested paths rise with K and falls with number of coda cycles, due to the increasing number of constraints on the path, particularly due to the fixed inputs