756 research outputs found
LIPIcs, Volume 251, ITCS 2023, Complete Volume
LIPIcs, Volume 251, ITCS 2023, Complete Volum
Towards trustworthy computing on untrustworthy hardware
Historically, hardware was thought to be inherently secure and trusted due to its
obscurity and the isolated nature of its design and manufacturing. In the last two
decades, however, hardware trust and security have emerged as pressing issues.
Modern day hardware is surrounded by threats manifested mainly in undesired
modifications by untrusted parties in its supply chain, unauthorized and pirated
selling, injected faults, and system and microarchitectural level attacks. These threats,
if realized, are expected to push hardware to abnormal and unexpected behaviour
causing real-life damage and significantly undermining our trust in the electronic and
computing systems we use in our daily lives and in safety critical applications. A
large number of detective and preventive countermeasures have been proposed in
literature. It is a fact, however, that our knowledge of potential consequences to
real-life threats to hardware trust is lacking given the limited number of real-life
reports and the plethora of ways in which hardware trust could be undermined. With
this in mind, run-time monitoring of hardware combined with active mitigation of
attacks, referred to as trustworthy computing on untrustworthy hardware, is proposed
as the last line of defence. This last line of defence allows us to face the issue of live
hardware mistrust rather than turning a blind eye to it or being helpless once it occurs.
This thesis proposes three different frameworks towards trustworthy computing
on untrustworthy hardware. The presented frameworks are adaptable to different
applications, independent of the design of the monitored elements, based on
autonomous security elements, and are computationally lightweight. The first
framework is concerned with explicit violations and breaches of trust at run-time,
with an untrustworthy on-chip communication interconnect presented as a potential
offender. The framework is based on the guiding principles of component guarding,
data tagging, and event verification. The second framework targets hardware elements
with inherently variable and unpredictable operational latency and proposes a
machine-learning based characterization of these latencies to infer undesired latency
extensions or denial of service attacks. The framework is implemented on a DDR3
DRAM after showing its vulnerability to obscured latency extension attacks. The
third framework studies the possibility of the deployment of untrustworthy hardware
elements in the analog front end, and the consequent integrity issues that might arise
at the analog-digital boundary of system on chips. The framework uses machine
learning methods and the unique temporal and arithmetic features of signals at this
boundary to monitor their integrity and assess their trust level
LIPIcs, Volume 261, ICALP 2023, Complete Volume
LIPIcs, Volume 261, ICALP 2023, Complete Volum
Undergraduate and Graduate Course Descriptions, 2023 Spring
Wright State University undergraduate and graduate course descriptions from Spring 2023
Universality for graphs of bounded degeneracy
Given a family of graphs, a graph is called
-universal if contains every graph of as a
subgraph. Following the extensive research on universal graphs of small size
for bounded-degree graphs, Alon asked what is the minimum number of edges that
a graph must have to be universal for the class of all -vertex graphs that
are -degenerate. In this paper, we answer this question up to a factor that
is polylogarithmic in Comment: 17 page
Low Power Memory/Memristor Devices and Systems
This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within
Establishing Herd Immunity is Hard Even in Simple Geometric Networks
We study the following model of disease spread in a social network. At first,
all individuals are either infected or healthy. Next, in discrete rounds, the
disease spreads in the network from infected to healthy individuals such that a
healthy individual gets infected if and only if a sufficient number of its
direct neighbours are already infected.
We represent the social network as a graph. Inspired by the real-world
restrictions in the current epidemic, especially by social and physical
distancing requirements, we restrict ourselves to networks that can be
represented as geometric intersection graphs.
We show that finding a minimal vertex set of initially infected individuals
to spread the disease in the whole network is computationally hard, already on
unit disk graphs. Hence, to provide some algorithmic results, we focus
ourselves on simpler geometric graph classes, such as interval graphs and grid
graphs.Comment: This is an extended and revised version of a preliminary conference
report that was presented in WAW 202
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