9,557 research outputs found
A multi-paradigm language for reactive synthesis
This paper proposes a language for describing reactive synthesis problems
that integrates imperative and declarative elements. The semantics is defined
in terms of two-player turn-based infinite games with full information.
Currently, synthesis tools accept linear temporal logic (LTL) as input, but
this description is less structured and does not facilitate the expression of
sequential constraints. This motivates the use of a structured programming
language to specify synthesis problems. Transition systems and guarded commands
serve as imperative constructs, expressed in a syntax based on that of the
modeling language Promela. The syntax allows defining which player controls
data and control flow, and separating a program into assumptions and
guarantees. These notions are necessary for input to game solvers. The
integration of imperative and declarative paradigms allows using the paradigm
that is most appropriate for expressing each requirement. The declarative part
is expressed in the LTL fragment of generalized reactivity(1), which admits
efficient synthesis algorithms, extended with past LTL. The implementation
translates Promela to input for the Slugs synthesizer and is written in Python.
The AMBA AHB bus case study is revisited and synthesized efficiently,
identifying the need to reorder binary decision diagrams during strategy
construction, in order to prevent the exponential blowup observed in previous
work.Comment: In Proceedings SYNT 2015, arXiv:1602.0078
Lost in Abstraction: Monotonicity in Multi-Threaded Programs (Extended Technical Report)
Monotonicity in concurrent systems stipulates that, in any global state,
extant system actions remain executable when new processes are added to the
state. This concept is not only natural and common in multi-threaded software,
but also useful: if every thread's memory is finite, monotonicity often
guarantees the decidability of safety property verification even when the
number of running threads is unknown. In this paper, we show that the act of
obtaining finite-data thread abstractions for model checking can be at odds
with monotonicity: Predicate-abstracting certain widely used monotone software
results in non-monotone multi-threaded Boolean programs - the monotonicity is
lost in the abstraction. As a result, well-established sound and complete
safety checking algorithms become inapplicable; in fact, safety checking turns
out to be undecidable for the obtained class of unbounded-thread Boolean
programs. We demonstrate how the abstract programs can be modified into
monotone ones, without affecting safety properties of the non-monotone
abstraction. This significantly improves earlier approaches of enforcing
monotonicity via overapproximations
A method for generating UTS assignments with an iterative state transition algorithm
There is a lack of systematic procedures that can be used to find uni-code totally sequential (UTS) assignments from a flow table description of an asynchronous sequential circuit. Presented here is an iterative internal state assignment method. This method consists of three algorithms. The first generates a minimum variable initial assignment from a flow table description. The second tests the validity of this assignment by constructing minimum length transition paths without crossover and the third augments this assignment by adding an internal state variable in the event that all transition paths cannot be constructed without crossover. The second and the third algorithms are used iteratively until a valid non-universal UTS assignment is produced.
The iterative state assignment method is systematic in all its phases. Every phase of the method includes more than one algorithm to perform the same function. The algorithm producing minimum length transition paths is very powerful in that it can also be used in conjunction with other state assignment methods producing either universal or non-universal UTS assignments.
After one obtains a valid UTS assignment an algorithm is provided to replace some or all of the totally sequential transitions with mixed mode transitions. This reduces the number of subtransitions in a given transition path and therefore speeds up the transition time considerably --Abstract, page ii
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EXTEND-L : an input language for extensible register transfer compilation
This report discusses the model and input language for EXTEND, a synthesis system that permits extensible register transfer synthesis. EXTEND-L fills the need for a language that bridges the gap between existing behavioral input descriptions, which are too abstract, and structural schematics, which cannot capture the high-level behavior. The report first discusses previous work in behavioral synthesis and summarizes the deficiencies of these behavioral specifications. The report then describes the proposed langauge in detail, and concludes with a few examples that show its utility
A Team Based Variant of CTL
We introduce two variants of computation tree logic CTL based on team
semantics: an asynchronous one and a synchronous one. For both variants we
investigate the computational complexity of the satisfiability as well as the
model checking problem. The satisfiability problem is shown to be
EXPTIME-complete. Here it does not matter which of the two semantics are
considered. For model checking we prove a PSPACE-completeness for the
synchronous case, and show P-completeness for the asynchronous case.
Furthermore we prove several interesting fundamental properties of both
semantics.Comment: TIME 2015 conference version, modified title and motiviatio
Modelling and Simulation of Asynchronous Real-Time Systems using Timed Rebeca
In this paper we propose an extension of the Rebeca language that can be used
to model distributed and asynchronous systems with timing constraints. We
provide the formal semantics of the language using Structural Operational
Semantics, and show its expressiveness by means of examples. We developed a
tool for automated translation from timed Rebeca to the Erlang language, which
provides a first implementation of timed Rebeca. We can use the tool to set the
parameters of timed Rebeca models, which represent the environment and
component variables, and use McErlang to run multiple simulations for different
settings. Timed Rebeca restricts the modeller to a pure asynchronous
actor-based paradigm, where the structure of the model represents the service
oriented architecture, while the computational model matches the network
infrastructure. Simulation is shown to be an effective analysis support,
specially where model checking faces almost immediate state explosion in an
asynchronous setting.Comment: In Proceedings FOCLASA 2011, arXiv:1107.584
Synthesis heuristics for large asynchronous sequential circuits
Many well-known synthesis procedures for asynchronous sequential circuits produce minimal or near-minimal results, but are practical only for very small problems. These algorithms become unwieldy when applied to large circuits with, for example, three or more input variables and twenty or more internal states. New heuristic procedures are described which permit the synthesis of very large machines. Although the resulting designs are generally not minimal, the heuristics are able to produce near-minimal solutions orders of magnitude more rapidly than the minimal algorithms. A method for specifying sequential circuit behavior is presented. Input-output sequences define submachines or modules. When properly interconnected, these modules form the required sequential circuit. It is shown that the waveform and interconnection specifications may easily be translated into flow table form. A large flow table simplification heuristic is developed. The algorithm may be applied to tables having hundreds of rows, and handles both normal and non-normal mode circuit specifications. Nonstandard state assignment procedures for normal, fundamental mode asynchronous sequential circuits are examined. An algorithm for rapidly generating large flow table internal state assignments is proposed. The algorithms described have been programmed in PL/1 and incorporated into an automated design system for asynchronous circuits; the system also includes minimum and near-minimum variable state assignment generators, a code evaluation routine, a design equation generator, and two Boolean equation simplification procedures. Large sequential circuits designed using the system illustrate the utility of the heuristic procedures --Abstract, pages ii-iii
A State Assignment Procedure For Asynchronous Sequential Circuits
This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to dis. © 1971, IEEE. All rights reserved
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