New advances in synchronization of digital communication receivers

Synchronization is a challenging but very important task in communications. In digital communication systems, a hierarchy of synchronization problems has to be considered: carrier synchronization, symbol timing synchronization and frame synchronization. For bandwidth efficiency and burst transmission reasons, the former two synchronization steps tend to favor non-data aided (NDA or blind) techniques, while in general, the last one is usually solved by inserting repetitively known bits or words into the data sequence, and is referred to as a data-aided (DA) approach. Over the last two decades, extensive research work has been carried out to design nondata-aided timing recovery and carrier synchronization algorithms. Despite their importance and spread use, most of the existing blind synchronization algorithms are derived in an ad-hoc manner without exploiting optimally the entire available statistical information. In most cases their performance is evaluated by computer simulations, rigorous and complete performance analysis has not been performed yet. It turns out that a theoretical oriented approach is indispensable for studying the limit or bound of algorithms and comparing different methods. The main goal of this dissertation is to develop several novel signal processing frameworks that enable to analyze and improve the performance of the existing timing recovery and carrier synchronization algorithms. As byproducts of this analysis, unified methods for designing new computationally and statistically efficient (i.e., minimum variance estimators) blind feedforward synchronizers are developed. Our work consists of three tightly coupled research directions. First, a general and unified framework is proposed to develop optimal nonlinear least-squares (NLS) carrier recovery scheme for burst transmissions. A family of blind constellation-dependent optimal "matched" NLS carrier estimators is proposed for synchronization of burst transmissions fully modulated by PSK and QAM-constellations in additive white Gaussian noise channels. Second, a cyclostationary statistics based framework is proposed for designing computationally and statistically efficient robust blind symbol timing recovery for time-selective flat-fading channels. Lastly, dealing with the problem of frame synchronization, a simple and efficient data-aided approach is proposed for jointly estimating the frame boundary, the frequency-selective channel and the carrier frequency offset

Synchronization in all-digital QAM receivers

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection

Advanced DSP Techniques for High-Capacity and Energy-Efficient Optical Fiber Communications

The rapid proliferation of the Internet has been driving communication networks closer and closer to their limits, while available bandwidth is disappearing due to an ever-increasing network load. Over the past decade, optical fiber communication technology has increased per fiber data rate from 10 Tb/s to exceeding 10 Pb/s. The major explosion came after the maturity of coherent detection and advanced digital signal processing (DSP). DSP has played a critical role in accommodating channel impairments mitigation, enabling advanced modulation formats for spectral efficiency transmission and realizing flexible bandwidth. This book aims to explore novel, advanced DSP techniques to enable multi-Tb/s/channel optical transmission to address pressing bandwidth and power-efficiency demands. It provides state-of-the-art advances and future perspectives of DSP as well