UML as a system level design methodology with application to software radio

Master'sMASTER OF SCIENC

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Strategic directions in constraint programming

An abstract is not available

Constraint-based Programming: A Survey

Report on constraint-based computer programming analyzing finite-domain and continuous-domain constraint satisfaction methods and existing systems which apply constraints to problem-solving, modeling, and simulation

Automatic generation of protocol converters from scenario-based specifications

Master'sMASTER OF SCIENC