Implementation of a real time Hough transform using FPGA technology

This thesis is concerned with the modelling, design and implementation of efficient architectures for performing the Hough Transform (HT) on mega-pixel resolution real-time images using Field Programmable Gate Array (FPGA) technology. Although the HT has been around for many years and a number of algorithms have been developed it still remains a significant bottleneck in many image processing applications. Even though, the basic idea of the HT is to locate curves in an image that can be parameterized: e.g. straight lines, polynomials or circles, in a suitable parameter space, the research presented in this thesis will focus only on location of straight lines on binary images. The HT algorithm uses an accumulator array (accumulator bins) to detect the existence of a straight line on an image. As the image needs to be binarized, a novel generic synchronization circuit for windowing operations was designed to perform edge detection. An edge detection method of special interest, the canny method, is used and the design and implementation of it in hardware is achieved in this thesis. As each image pixel can be implemented independently, parallel processing can be performed. However, the main disadvantage of the HT is the large storage and computational requirements. This thesis presents new and state-of-the-art hardware implementations for the minimization of the computational cost, using the Hybrid-Logarithmic Number System (Hybrid-LNS) for calculating the HT for fixed bit-width architectures. It is shown that using the Hybrid-LNS the computational cost is minimized, while the precision of the HT algorithm is maintained. Advances in FPGA technology now make it possible to implement functions as the HT in reconfigurable fabrics. Methods for storing large arrays on FPGA’s are presented, where data from a 1024 x 1024 pixel camera at a rate of up to 25 frames per second are processed

Performance Analysis of Hardware/Software Co-Design of Matrix Solvers

Solving a system of linear and nonlinear equations lies at the heart of many scientific and engineering applications such as circuit simulation, applications in electric power networks, and structural analysis. The exponentially increasing complexity of these computing applications and the high cost of supercomputing force us to explore affordable high performance computing platforms. The ultimate goal of this research is to develop hardware friendly parallel processing algorithms and build cost effective high performance parallel systems using hardware in order to enable the solution of large linear systems. In this thesis, FPGA-based general hardware architectures of selected iterative methods and direct methods are discussed. Xilinx Embedded Development Kit (EDK) hardware/software (HW/SW) codesigns of these methods are also presented. For iterative methods, FPGA based hardware architectures of Jacobi, combined Jacobi and Gauss-Seidel, and conjugate gradient (CG) are proposed. The convergence analysis of the LNS-based Jacobi processor demonstrates to what extent the hardware resource constraints and additional conversion error affect the convergence of Jacobi iterative method. Matlab simulations were performed to compare the performance of three iterative methods in three ways, i.e., number of iterations for any given tolerance, number of iterations for different matrix sizes, and computation time for different matrix sizes. The simulation results indicate that the key to a fast implementation of the three methods is a fast implementation of matrix multiplication. The simulation results also show that CG method takes less number of iterations for any given tolerance, but more computation time as matrix size increases compared to other two methods, since matrix-vector multiplication is a more dominant factor in CG method than in the other two methods. By implementing matrix multiplications of the three methods in hardware with Xilinx EDK HW/SW codesign, the performance is significantly improved over pure software Power PC (PPC) based implementation. The EDK implementation results show that CG takes less computation time for any size of matrices compared to other two methods in HW/SW codesign, due to that fact that matrix multiplications dominate the computation time of all three methods while CG requires less number of iterations to converge compared to other two methods. For direct methods, FPGA-based general hardware architecture and Xilinx EDK HW/SW codesign of WZ factorization are presented. Single unit and scalable hardware architectures of WZ factorization are proposed and analyzed under different constraints. The results of Matlab simulations show that WZ runs faster than the LU on parallel processors but slower on a single processor. The simulation results also indicate that the most time consuming part of WZ factorization is matrix update. By implementing the matrix update of WZ factorization in hardware with Xilinx EDK HW/SW codesign, the performance is also apparently improved over PPC based pure software implementation

Advances and Novel Approaches in Discrete Optimization

Discrete optimization is an important area of Applied Mathematics with a broad spectrum of applications in many fields. This book results from a Special Issue in the journal Mathematics entitled ‘Advances and Novel Approaches in Discrete Optimization’. It contains 17 articles covering a broad spectrum of subjects which have been selected from 43 submitted papers after a thorough refereeing process. Among other topics, it includes seven articles dealing with scheduling problems, e.g., online scheduling, batching, dual and inverse scheduling problems, or uncertain scheduling problems. Other subjects are graphs and applications, evacuation planning, the max-cut problem, capacitated lot-sizing, and packing algorithms

Defect energies, band alignments, and charge carrier recombination in polycrystalline Cu(In,Ga)(Se,S)2 alloys

This work investigates the defect energies, band alignments, and charge carrier recombination in polycrystalline Cu(In1-xGax)(Se1-ySy)2 chalcopyrite thin films and the interrelationship with the alloy composition. Photoluminescence spectroscopy of investigated Cu-poor Cu(In,Ga)(Se,S)2 layers generally shows broad emission lines with the corresponding maxima shifting towards higher energies under decreasing temperature or under increasing excitation power. Admittance spectroscopy of Cu-poor ZnO/CdS/Cu(In,Ga)(Se,S)2 chalcopyrite devices shows that the activation energies of the dominant defect distributions involving donors at the CdS/absorber interface and deep acceptors in the chalcopyrite bulk, increase upon alloying CuInSe2 with S. The band alignments within the Cu(In1-xGax)(Se1-ySy)2 system are determined using the energy position of the bulk acceptor state as a reference. The band gap enlargement under Ga alloying is accommodated almost exclusively in the rise of the conduction band edge, whereas the increase of band gap upon alloying with S is shared between comparable valence and conduction band offsets. The extrapolated band discontinuities [delta]EV(CuInSe2/CuInS2) = -0.23 eV, [delta]EC(CuInSe2/CuInS2) = 0.21 eV, [delta]EV(CuInSe2/CuGaSe2) = 0.036 eV, and [delta]EC(CuInSe2/CuGaSe2) = 0.7 eV are in good agreement with theoretical predictions. Current-voltage analysis of Cu-poor ZnO/CdS/Cu(In,Ga)(Se,S)2 devices reveals recombination barriers which follow the band gap energy of the absorber irrespective of alloy composition, as expected for dominant recombination in the chalcopyrite bulk. In turn, the recombination at the active junction interface prevails in Cu-rich devices which display substantially smaller barriers when compared to the band gap energy of the absorber. The result indicates that the Cu-stoichiometry is the driving compositional parameter for the charge carrier recombination in the chalcopyrite heterojunctions under investigations