Test and security in a System-on-Chip environment

This dissertation outlines new approaches for test and security in a System-on-Chip (SoC) environment. A methodology is proposed for designing a single test access mechanism (TAM) architecture on each die with a "bandwidth adapter" that allows it to be efficiently used for multiple different test data bandwidths in three-dimensional integrated circuits (3D-IC) using through-silicon vias (TSVs). In this way, a single test architecture can be re-used for pre-bond, partial stack, and post-bond testing while minimizing test time across all phases of test. Unlike previous approaches, this methodology does not need multiple TAM architectures or reconfigurable wrappers in order to be efficient when the test data bandwidth changes. In industry, sequential linear decompression is widely used to reduce data and bandwidth requirements. A new scheme using a multiple polynomial linear feedback shift register (LFSR) with rotating polynomial is proposed here to increase encoding flexibility resulting in higher compression ratios. An algorithm is described to assign test cubes to polynomials in a way that enhances encoding efficiency. For hardware security, a new attack strategy against logic obfuscation is described here. It is based on applying brute force iteratively to each logic cone one at a time and is shown to significantly reduce the number of brute force key combinations that need to be tried by an attacker. It is shown that inserting key gates based on MUXes is an effective approach to increase security against this type of attack. In data security for hardware, existing techniques for computing with encrypted operands are either prohibitively expense (e.g., fully homomorphic encryption) or only work for special cases (e.g., linear circuits). A lightweight scheme implemented at the gate-level is proposed for computing with noise-obfuscated data. By carefully selecting internal locations for noise cancellation in arbitrary logic circuits, the overhead can be greatly minimized. One important application of the proposed scheme is for protecting data inside a computing unit obtained from a third party IP provider where a hidden backdoor access mechanism or hardware Trojan could be maliciously inserted.Electrical and Computer Engineerin

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>Dissertatio

Accelerating scientific applications on GPUs

We have analyzed and accelerated two large scientific applications used at the Barcelona Supercomputer Center (BSC). With this, we want to show how two complex applications can be efficiently ported to GPUs. In addition, we have developed a mechanism to manage the coherency of CPU/GPU memories

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Secure HfO2 based charge trap EEPROM with lifetime and data retention time modeling

Trusted computing is currently the most promising security strategy for cyber physical systems. Trusted computing platform relies on securely stored encryption keys in the on-board memory. However, research and actual cases have shown the vulnerability of the on-board memory to physical cryptographic attacks. This work proposed an embedded secure EEPROM architecture employing charge trap transistor to improve the security of storage means in the trusted computing platform. The charge trap transistor is CMOS compatible with high dielectric constant material as gate oxide which can trap carriers. The process compatibility allows the secure information containing memory to be embedded with the CPU. This eliminates the eavesdropping and optical observation. This effort presents the secure EEPROM cell, its high voltage programming control structure and an interface architecture for command and data communication between the EEPROM and CPU. The interface architecture is an ASIC based design that exclusively for the secure EEPROM. The on-board programming capability enables adjustment of programming voltages and accommodates EEPROM threshold variation due to PVT to optimize lifetime. In addition to the functional circuitry, this work presents the first model of lifetime and data retention time tradeoff for this new type of EEPROM. This model builds the bridge between desired data retention time and lifetime while producing the corresponding programming time and voltage

Physical design methodologies for monolithic 3D ICs

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.Ph.D

Engineering Education and Research Using MATLAB

MATLAB is a software package used primarily in the field of engineering for signal processing, numerical data analysis, modeling, programming, simulation, and computer graphic visualization. In the last few years, it has become widely accepted as an efficient tool, and, therefore, its use has significantly increased in scientific communities and academic institutions. This book consists of 20 chapters presenting research works using MATLAB tools. Chapters include techniques for programming and developing Graphical User Interfaces (GUIs), dynamic systems, electric machines, signal and image processing, power electronics, mixed signal circuits, genetic programming, digital watermarking, control systems, time-series regression modeling, and artificial neural networks

Development of MEMS Piezoelectric Vibration Energy Harvesters with Wafer-Level Integrated Tungsten Proof-Mass for Ultra Low Power Autonomous Wireless Sensors

La génération d’énergie localisée et à petite échelle, par transformation de l’énergie vibratoire disponible dans l’environnement, est une solution attrayante pour améliorer l’autonomie de certains noeuds de capteurs sans-fil pour l’Internet des objets (IoT). Grâce à des microdispositifs inertiels résonants piézoélectriques, il est possible de transformer l’énergie mécanique en électricité. Cette thèse présente une étude exhaustive de cette technologie et propose un procédé pour fabriquer des microgénérateurs MEMS offrant des performances surpassant l’état de l’art. On présente d’abord une revue complète des limites physiques et technologiques pour identifier le meilleur chemin d’amélioration. En évaluant les approches proposées dans la littérature (géométrie, architecture, matériaux, circuits, etc.), nous suggérons des métriques pour comparer l’état de l’art. Ces analyses démontrent que la limite fondamentale est l’énergie absorbée par le dispositif, car plusieurs des solutions existantes répondent déjà aux autres limites. Pour un générateur linéaire résonant, l’absorption d’énergie dépend donc des vibrations disponibles, mais aussi de la masse du dispositif et de son facteur de qualité. Pour orienter la conception de prototypes, nous avons réalisé une étude sur le potentiel des capteurs autonomes dans une automobile. Nous avons évalué une liste des capteurs présents sur un véhicule pour leur compatibilité avec cette technologie. Nos mesures de vibrations sur un véhicule en marche aux emplacements retenus révèlent que l’énergie disponible pour un dispositif linéaire résonant MEMS se situe entre 30 à 150 Hz. Celui-ci pourrait produire autour de 1 à 10 μW par gramme. Pour limiter la taille d’un générateur MEMS pouvant produire 10 μW, il faut une densité supérieure à celle du silicium, ce qui motive l’intégration du tungstène. L’effet du tungstène sur la sensibilité du dispositif est évident, mais nous démontrons également que l’usage de ce matériau permet de réduire l’impact de l’amortissement fluidique sur le facteur de qualité mécanique Qm. En fait, lorsque l’amortissement fluidique domine, ce changement peut améliorer Qm d’un ordre de grandeur, passant de 103 à 104 dans l’air ambiant. Par conséquent, le rendement du dispositif est amélioré sans utiliser un boîtier sous vide. Nous proposons ensuite un procédé de fabrication qui intègre au niveau de la tranche des masses de tungstène de 500 μm d’épais. Ce procédé utilise des approches de collage de tranches et de gravure humide du métal en deux étapes. Nous présentons chaque bloc de fabrication réalisé pour démontrer la faisabilité du procédé, lequel a permis de fabriquer plusieurs prototypes. Ces dispositifs ont été testés en laboratoire, certains démontrant des performances records en terme de densité de puissance normalisée. Notre meilleur design se démarque par une métrique de 2.5 mW-s-1/(mm3(m/s2)2), soit le meilleur résultat répertorié dans l’état de l’art. Avec un volume de 3.5 mm3, il opère à 552.7 Hz et produit 2.7 μW à 1.6 V RMS à partir d’une accélération de 1 m/s2. Ces résultats démontrent que l’intégration du tungstène dans les microgénérateurs MEMS est très avantageuse et permet de s’approcher davantage des requis des applications réelles.Small scale and localized power generation, using vibration energy harvesting, is considered as an attractive solution to enhance the autonomy of some wireless sensor nodes used in the Internet of Things (IoT). Conversion of the ambient mechanical energy into electricity is most often done through inertial resonant piezoelectric microdevices. This thesis presents an extensive study of this technology and proposes a process to fabricate MEMS microgenerators with record performances compared to the state of the art. We first present a complete review of the physical and technological limits of this technology to asses the best path of improvement. Reported approaches (geometries, architectures, materials, circuits) are evaluated and figures of merit are proposed to compare the state of the art. These analyses show that the fundamental limit is the absorbed energy, as most proposals to date partially address the other limits. The absorbed energy depends on the level of vibrations available, but also on the mass of the device and its quality factor for a linear resonant generator. To guide design of prototypes, we conducted a study on the potential of autonomous sensors in vehicles. A survey of sensors present on a car was realized to estimate their compatibility with energy harvesting technologies. Vibration measurements done on a running vehicle at relevant locations showed that the energy available for MEMS devices is mostly located in a frequency range of 30 to 150 Hz and could generate power in the range of 1-10 μW per gram from a linear resonator. To limit the size of a MEMS generator capable of producing 10 μW, a higher mass density compared to silicon is needed, which motivates the development of a process that incorporates tungsten. Although the effect of tungsten on the device sensitivity is well known, we also demonstrate that it reduces the impact of the fluidic damping on the mechanical quality factor Qm. If fluidic damping is dominant, switching to tungsten can improve Qm by an order of magnitude, going from 103 to 104 in ambient air. As a result, the device efficiency is improved despite the lack of a vacuum package. We then propose a fabrication process flow to integrate 500 μm thick tungsten masses at the wafer level. This process combines wafer bonding with a 2-step wet metal etching approach. We present each of the fabrication nodes realized to demonstrate the feasibility of the process, which led to the fabrication of several prototypes. These devices are tested in the lab, with some designs demonstrating record breaking performances in term of normalized power density. Our best design is noteworthy for its figure of merit that is around 2.5 mW-s-1/(mm3(m/s2)2), which is the best reported in the state of the art. With a volume of 3.5 mm3, it operates at 552.7 Hz and produces 2.7 μW at 1.6 V RMS from an acceleration of 1 m/s2. These results therefore show that tungsten integration in MEMS microgenerators is very advantageous, allowing to reduce the gap with needs of current applications

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields